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Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc

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  Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc Wolfram Sang <wsa@the-dreams.de> - 2016-04-14 20:50 +0200
    Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc Heiko Stübner <heiko@sntech.de> - 2016-04-15 09:40 +0200
      Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc "David.Wu" <david.wu@rock-chips.com> - 2016-04-15 14:20 +0200
    Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc "David.Wu" <david.wu@rock-chips.com> - 2016-04-15 14:20 +0200
      Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc Wolfram Sang <wsa@the-dreams.de> - 2016-04-15 20:00 +0200
        Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc "David.Wu" <david.wu@rock-chips.com> - 2016-04-18 15:20 +0200

#1379217 — Re: [PATCH v5 2/2] i2c: rk3x: add i2c support for rk3399 soc

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> + - input-clk-rate : frequency rate of function clock used(in Hz). If omitted,
> +	the default clock rate is used. It is just used at rk3399 soc.

Why is this needed? Why don't we simply use the default or calculate the
best value somehow?

> + * @t_calc: Caculated rk3x private timings  that would
> + * be written into regs

double space

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#1379513

David,

Am Donnerstag, 14. April 2016, 20:48:48 schrieb Wolfram Sang:
> > + - input-clk-rate : frequency rate of function clock used(in Hz). If
> > omitted, +	the default clock rate is used. It is just used at rk3399 soc.
> 
> Why is this needed? Why don't we simply use the default or calculate the
> best value somehow?

if you need to _get_ the clock-rate, clk_get_rate is the abvious choice and if 
you need to _set_ some specific rate, I guess it should be done via the 
assigned-clocks mechanism in the devicetree - see veyron dts files that already 
do this for some other parts.

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#1379778

Hi Heiko,

在 2016/4/15 15:31, Heiko Stübner 写道:
> David,
>
> Am Donnerstag, 14. April 2016, 20:48:48 schrieb Wolfram Sang:
>>> + - input-clk-rate : frequency rate of function clock used(in Hz). If
>>> omitted, +	the default clock rate is used. It is just used at rk3399 soc.
>> Why is this needed? Why don't we simply use the default or calculate the
>> best value somehow?
> if you need to _get_ the clock-rate, clk_get_rate is the abvious choice and if
> you need to _set_ some specific rate, I guess it should be done via the
> assigned-clocks mechanism in the devicetree - see veyron dts files that already
> do this for some other parts.

Okay, i will try it, thank you.

>
>
>
>

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#1379780

Hi Wolfram,

在 2016/4/15 2:48, Wolfram Sang 写道:
>> + - input-clk-rate : frequency rate of function clock used(in Hz). If omitted,
>> +	the default clock rate is used. It is just used at rk3399 soc.
> Why is this needed? Why don't we simply use the default or calculate the
> best value somehow?
The default frequency rate of function clock is 50M Hz, it can match F/S 
mode,
but HS mode not. If use default rate 50M to get 1.7M scl-frequency rate 
, we could not
get accurately 1.7M frequecy rate. The input-clk-rate is more higher, we 
get more
accurately scl-frequency rate,  as 200M is a suitable input-clk-rate.

If 200M was used for F/S mode, it would increase power consumption, so 
add a option that
could be configured from DT.

>> + * @t_calc: Caculated rk3x private timings  that would
>> + * be written into regs
> double space
>

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#1380070

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> The default frequency rate of function clock is 50M Hz, it can match
> F/S mode, but HS mode not. If use default rate 50M to get 1.7M
> scl-frequency rate , we could not get accurately 1.7M frequecy rate.
> The input-clk-rate is more higher, we get more accurately
> scl-frequency rate,  as 200M is a suitable input-clk-rate.
> 
> If 200M was used for F/S mode, it would increase power consumption, so
> add a option that could be configured from DT.

If I understand you correctly, couldn't you use clk_set_rate() depending
on the desired scl frequency which is already described in DT as
clock-frequency?

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#1381688

Hi Wolfram，

在 2016/4/16 1:58, Wolfram Sang 写道:
>> The default frequency rate of function clock is 50M Hz, it can match
>> F/S mode, but HS mode not. If use default rate 50M to get 1.7M
>> scl-frequency rate , we could not get accurately 1.7M frequecy rate.
>> The input-clk-rate is more higher, we get more accurately
>> scl-frequency rate,  as 200M is a suitable input-clk-rate.
>>
>> If 200M was used for F/S mode, it would increase power consumption, so
>> add a option that could be configured from DT.
> If I understand you correctly, couldn't you use clk_set_rate() depending
> on the desired scl frequency which is already described in DT as
> clock-frequency?

Yeap, the default input clock rate is too low for HS mode, and it 's 
flexible that
we get it from DT.

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