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[PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

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  [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Kedareswara rao Appana <appana.durga.rao@xilinx.com> - 2016-04-15 11:00 +0200
    Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma  device tree binding documentation Rob Herring <robh@kernel.org> - 2016-04-21 15:50 +0200
      RE: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma  device tree binding documentation Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> - 2016-04-22 07:40 +0200
        Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma  device tree binding documentation Rob Herring <robh@kernel.org> - 2016-04-22 18:20 +0200
          RE: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma  device tree binding documentation Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> - 2016-04-22 18:50 +0200

#1379562 — [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

Device-tree binding documentation for Xilinx zynqmp dma engine used in
Zynq UltraScale+ MPSoC.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
---
Changes in v6:
- Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
  from the binding doc as it allow broken combinations when dma-coherent
  is set as suggested by Rob.
- Fixed minor comments given by Rob related coding(lower case DT node name).
Changes in v5:
- Use dma-coherent flag for coherent transfers as suggested by rob.
- Removed unnecessary properties from binding doc as suggested by Rob.
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None.

 .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt

diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
new file mode 100644
index 0000000..f0f0b54
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
@@ -0,0 +1,44 @@
+Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Required properties:
+- compatible		: Should be "xlnx,zynqmp-dma-1.0"
+- reg			: Memory map for gdma/adma module access.
+- interrupt-parent	: Interrupt controller the interrupt is routed through
+- interrupts		: Should contain DMA channel interrupt.
+- xlnx,bus-width	: Axi buswidth in bits. Should contain 128 or 64
+- clock-names		: List of input clocks "clk_main", "clk_apb"
+			  (see clock bindings for details)
+
+Optional properties:
+- xlnx,include-sg	: Indicates the controller to operate in simple or
+			  scatter gather dma mode
+- xlnx,ratectrl		: Scheduling interval in terms of clock cycles for
+			  source AXI transaction
+- xlnx,overfetch	: Tells whether the channel is allowed to over
+			  fetch the data
+- xlnx,src-issue	: Number of AXI outstanding transactions on source side
+- xlnx,src-burst-len	: AXI length for data read. Support only power of
+			  2 byte values.
+- xlnx,dst-burst-len	: AXI length for data write. Support only power of
+			  2 byte values.
+- dma-coherent		: Present if dma operations are coherent.
+
+Example:
+++++++++
+fpd_dma_chan1: dma@fd500000 {
+	compatible = "xlnx,zynqmp-dma-1.0";
+	reg = <0x0 0xFD500000 0x1000>;
+	interrupt-parent = <&gic>;
+	interrupts = <0 117 4>;
+	clock-names = "clk_main", "clk_apb";
+	xlnx,bus-width = <128>;
+	xlnx,include-sg;
+	xlnx,overfetch;
+	dma-coherent;
+	xlnx,ratectrl = <0>;
+	xlnx,src-issue = <16>;
+	xlnx,src-burst-len = <4>;
+	xlnx,dst-burst-len = <4>;
+};
-- 
2.1.2

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#1384238 — Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

On Fri, Apr 15, 2016 at 02:22:53PM +0530, Kedareswara rao Appana wrote:
> Device-tree binding documentation for Xilinx zynqmp dma engine used in
> Zynq UltraScale+ MPSoC.
> 
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
> ---
> Changes in v6:
> - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
>   from the binding doc as it allow broken combinations when dma-coherent
>   is set as suggested by Rob.
> - Fixed minor comments given by Rob related coding(lower case DT node name).
> Changes in v5:
> - Use dma-coherent flag for coherent transfers as suggested by rob.
> - Removed unnecessary properties from binding doc as suggested by Rob.
> Changes in v4:
> - None
> Changes in v3:
> - None
> Changes in v2:
> - None.
> 
>  .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  | 44 ++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> 
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> new file mode 100644
> index 0000000..f0f0b54
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> @@ -0,0 +1,44 @@
> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
> +memory to device and device to memory transfers. It also has flow
> +control and rate control support for slave/peripheral dma access.
> +
> +Required properties:
> +- compatible		: Should be "xlnx,zynqmp-dma-1.0"
> +- reg			: Memory map for gdma/adma module access.
> +- interrupt-parent	: Interrupt controller the interrupt is routed through
> +- interrupts		: Should contain DMA channel interrupt.
> +- xlnx,bus-width	: Axi buswidth in bits. Should contain 128 or 64

I think how this is getting used by the driver is wrong. 
{src,dst}_addr_widths are supposed to be a bitmask of supported slave 
device register widths. You aren't doing a bitmask and you are also 
saying you only support slaves with 8 or 16 byte data registers which is 
somewhat rare. It may happen to work because 128/8 == BIT(4). However, 
the documentation for the field is contradictory in that it says 1,2,4 
or 8 byte widths are supported, but the enum has more sizes.

Rob

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#1384701 — RE: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

Hi Rob,

	Thanks for the review...

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Thursday, April 21, 2016 7:12 PM
> To: Appana Durga Kedareswara Rao <appanad@xilinx.com>
> Cc: pawel.moll@arm.com; mark.rutland@arm.com;
> ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Michal Simek
> <michals@xilinx.com>; Soren Brinkmann <sorenb@xilinx.com>;
> vinod.koul@intel.com; dan.j.williams@intel.com; Appana Durga Kedareswara
> Rao <appanad@xilinx.com>; moritz.fischer@ettus.com;
> laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha
> Sarangi <anirudh@xilinx.com>; Punnaiah Choudary Kalluri
> <punnaia@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> dmaengine@vger.kernel.org
> Subject: Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma
> device tree binding documentation
> 
> On Fri, Apr 15, 2016 at 02:22:53PM +0530, Kedareswara rao Appana wrote:
> > Device-tree binding documentation for Xilinx zynqmp dma engine used in
> > Zynq UltraScale+ MPSoC.
> >
> > Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> > Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
> > ---
> > Changes in v6:
> > - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
> >   from the binding doc as it allow broken combinations when dma-coherent
> >   is set as suggested by Rob.
> > - Fixed minor comments given by Rob related coding(lower case DT node
> name).
> > Changes in v5:
> > - Use dma-coherent flag for coherent transfers as suggested by rob.
> > - Removed unnecessary properties from binding doc as suggested by Rob.
> > Changes in v4:
> > - None
> > Changes in v3:
> > - None
> > Changes in v2:
> > - None.
> >
> >  .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  | 44
> ++++++++++++++++++++++
> >  1 file changed, 44 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> >
> > diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> > new file mode 100644
> > index 0000000..f0f0b54
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> > @@ -0,0 +1,44 @@
> > +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
> > +memory to device and device to memory transfers. It also has flow
> > +control and rate control support for slave/peripheral dma access.
> > +
> > +Required properties:
> > +- compatible		: Should be "xlnx,zynqmp-dma-1.0"
> > +- reg			: Memory map for gdma/adma module access.
> > +- interrupt-parent	: Interrupt controller the interrupt is routed through
> > +- interrupts		: Should contain DMA channel interrupt.
> > +- xlnx,bus-width	: Axi buswidth in bits. Should contain 128 or 64
> 
> I think how this is getting used by the driver is wrong.
> {src,dst}_addr_widths are supposed to be a bitmask of supported slave
> device register widths. You aren't doing a bitmask and you are also
> saying you only support slaves with 8 or 16 byte data registers which is
> somewhat rare. It may happen to work because 128/8 == BIT(4). However,
> the documentation for the field is contradictory in that it says 1,2,4
> or 8 byte widths are supported, but the enum has more sizes.


The DMA supports an AXI bus width of 128/64 bits only.
Please refer IP data sheet. http://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Page No: 359(DMA Over fetch section).

That's why during probe we are making the dma_device supported source and destination address widths accordingly based on the DT property.

Snap shot of driver code from the probe:
       struct dma_device *p; 
       p->dst_addr_widths = zdev->chan->bus_width / 8;
       p->src_addr_widths = zdev->chan->bus_width / 8;

Where bus_width property is read from the probe.
err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width)

Cheers!,
Kedar...

> 
> Rob

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#1385332 — Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

On Fri, Apr 22, 2016 at 12:36 AM, Appana Durga Kedareswara Rao
<appana.durga.rao@xilinx.com> wrote:
> Hi Rob,
>
>         Thanks for the review...
>
>> -----Original Message-----
>> From: Rob Herring [mailto:robh@kernel.org]
>> Sent: Thursday, April 21, 2016 7:12 PM
>> To: Appana Durga Kedareswara Rao <appanad@xilinx.com>
>> Cc: pawel.moll@arm.com; mark.rutland@arm.com;
>> ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Michal Simek
>> <michals@xilinx.com>; Soren Brinkmann <sorenb@xilinx.com>;
>> vinod.koul@intel.com; dan.j.williams@intel.com; Appana Durga Kedareswara
>> Rao <appanad@xilinx.com>; moritz.fischer@ettus.com;
>> laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha
>> Sarangi <anirudh@xilinx.com>; Punnaiah Choudary Kalluri
>> <punnaia@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
>> dmaengine@vger.kernel.org
>> Subject: Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma
>> device tree binding documentation
>>
>> On Fri, Apr 15, 2016 at 02:22:53PM +0530, Kedareswara rao Appana wrote:
>> > Device-tree binding documentation for Xilinx zynqmp dma engine used in
>> > Zynq UltraScale+ MPSoC.
>> >
>> > Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
>> > Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
>> > ---
>> > Changes in v6:
>> > - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
>> >   from the binding doc as it allow broken combinations when dma-coherent
>> >   is set as suggested by Rob.
>> > - Fixed minor comments given by Rob related coding(lower case DT node
>> name).
>> > Changes in v5:
>> > - Use dma-coherent flag for coherent transfers as suggested by rob.
>> > - Removed unnecessary properties from binding doc as suggested by Rob.
>> > Changes in v4:
>> > - None
>> > Changes in v3:
>> > - None
>> > Changes in v2:
>> > - None.
>> >
>> >  .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  | 44
>> ++++++++++++++++++++++
>> >  1 file changed, 44 insertions(+)
>> >  create mode 100644
>> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> > new file mode 100644
>> > index 0000000..f0f0b54
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
>> > @@ -0,0 +1,44 @@
>> > +Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
>> > +memory to device and device to memory transfers. It also has flow
>> > +control and rate control support for slave/peripheral dma access.
>> > +
>> > +Required properties:
>> > +- compatible               : Should be "xlnx,zynqmp-dma-1.0"
>> > +- reg                      : Memory map for gdma/adma module access.
>> > +- interrupt-parent : Interrupt controller the interrupt is routed through
>> > +- interrupts               : Should contain DMA channel interrupt.
>> > +- xlnx,bus-width   : Axi buswidth in bits. Should contain 128 or 64
>>
>> I think how this is getting used by the driver is wrong.
>> {src,dst}_addr_widths are supposed to be a bitmask of supported slave
>> device register widths. You aren't doing a bitmask and you are also
>> saying you only support slaves with 8 or 16 byte data registers which is
>> somewhat rare. It may happen to work because 128/8 == BIT(4). However,
>> the documentation for the field is contradictory in that it says 1,2,4
>> or 8 byte widths are supported, but the enum has more sizes.
>
>
> The DMA supports an AXI bus width of 128/64 bits only.
> Please refer IP data sheet. http://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Page No: 359(DMA Over fetch section).

I understand that. That should not really matter if the AXI master
properly sets byte lane strobes other than defining max burst length
which you already have defined elsewhere.

> That's why during probe we are making the dma_device supported source and destination address widths accordingly based on the DT property.
>
> Snap shot of driver code from the probe:
>        struct dma_device *p;
>        p->dst_addr_widths = zdev->chan->bus_width / 8;
>        p->src_addr_widths = zdev->chan->bus_width / 8;

Read what I wrote before and read the documentation for these fields.
They are bitmasks.

Rob

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#1385350 — RE: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation

Hi Rob,

> -----Original Message-----
> From: dmaengine-owner@vger.kernel.org [mailto:dmaengine-
> owner@vger.kernel.org] On Behalf Of Rob Herring
> Sent: Friday, April 22, 2016 9:43 PM
> To: Appana Durga Kedareswara Rao <appanad@xilinx.com>
> Cc: pawel.moll@arm.com; mark.rutland@arm.com;
> ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Michal Simek
> <michals@xilinx.com>; Soren Brinkmann <sorenb@xilinx.com>;
> vinod.koul@intel.com; dan.j.williams@intel.com; moritz.fischer@ettus.com;
> laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha
> Sarangi <anirudh@xilinx.com>; Punnaiah Choudary Kalluri
> <punnaia@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> dmaengine@vger.kernel.org
> Subject: Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma
> device tree binding documentation
> 
> On Fri, Apr 22, 2016 at 12:36 AM, Appana Durga Kedareswara Rao
> <appana.durga.rao@xilinx.com> wrote:
> > Hi Rob,
> >
> >         Thanks for the review...
> >
> >> -----Original Message-----
> >> From: Rob Herring [mailto:robh@kernel.org]
> >> Sent: Thursday, April 21, 2016 7:12 PM
> >> To: Appana Durga Kedareswara Rao <appanad@xilinx.com>
> >> Cc: pawel.moll@arm.com; mark.rutland@arm.com;
> >> ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Michal Simek
> >> <michals@xilinx.com>; Soren Brinkmann <sorenb@xilinx.com>;
> >> vinod.koul@intel.com; dan.j.williams@intel.com; Appana Durga
> >> Kedareswara Rao <appanad@xilinx.com>; moritz.fischer@ettus.com;
> >> laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha
> >> Sarangi <anirudh@xilinx.com>; Punnaiah Choudary Kalluri
> >> <punnaia@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> >> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> >> dmaengine@vger.kernel.org
> >> Subject: Re: [PATCH v6 1/2] Documentation: DT: dma: Add Xilinx zynqmp
> >> dma device tree binding documentation
> >>
> >> On Fri, Apr 15, 2016 at 02:22:53PM +0530, Kedareswara rao Appana wrote:
> >> > Device-tree binding documentation for Xilinx zynqmp dma engine used
> >> > in Zynq UltraScale+ MPSoC.
> >> >
> >> > Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> >> > Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
> >> > ---
> >> > Changes in v6:
> >> > - Removed desc-axi-cache/dst-axi-cache/src-axi-cache properties
> >> >   from the binding doc as it allow broken combinations when dma-coherent
> >> >   is set as suggested by Rob.
> >> > - Fixed minor comments given by Rob related coding(lower case DT
> >> > node
> >> name).
> >> > Changes in v5:
> >> > - Use dma-coherent flag for coherent transfers as suggested by rob.
> >> > - Removed unnecessary properties from binding doc as suggested by Rob.
> >> > Changes in v4:
> >> > - None
> >> > Changes in v3:
> >> > - None
> >> > Changes in v2:
> >> > - None.
> >> >
> >> >  .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt  | 44
> >> ++++++++++++++++++++++
> >> >  1 file changed, 44 insertions(+)
> >> >  create mode 100644
> >> Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> >> >
> >> > diff --git
> >> > a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> >> b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> >> > new file mode 100644
> >> > index 0000000..f0f0b54
> >> > --- /dev/null
> >> > +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt
> >> > @@ -0,0 +1,44 @@
> >> > +Xilinx ZynqMP DMA engine, it does support memory to memory
> >> > +transfers, memory to device and device to memory transfers. It
> >> > +also has flow control and rate control support for slave/peripheral dma
> access.
> >> > +
> >> > +Required properties:
> >> > +- compatible               : Should be "xlnx,zynqmp-dma-1.0"
> >> > +- reg                      : Memory map for gdma/adma module access.
> >> > +- interrupt-parent : Interrupt controller the interrupt is routed through
> >> > +- interrupts               : Should contain DMA channel interrupt.
> >> > +- xlnx,bus-width   : Axi buswidth in bits. Should contain 128 or 64
> >>
> >> I think how this is getting used by the driver is wrong.
> >> {src,dst}_addr_widths are supposed to be a bitmask of supported slave
> >> device register widths. You aren't doing a bitmask and you are also
> >> saying you only support slaves with 8 or 16 byte data registers which
> >> is somewhat rare. It may happen to work because 128/8 == BIT(4).
> >> However, the documentation for the field is contradictory in that it
> >> says 1,2,4 or 8 byte widths are supported, but the enum has more sizes.
> >
> >
> > The DMA supports an AXI bus width of 128/64 bits only.
> > Please refer IP data sheet.
> http://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-
> ultrascale-trm.pdf Page No: 359(DMA Over fetch section).
> 
> I understand that. That should not really matter if the AXI master properly sets
> byte lane strobes other than defining max burst length which you already have
> defined elsewhere.
> 
> > That's why during probe we are making the dma_device supported source and
> destination address widths accordingly based on the DT property.
> >
> > Snap shot of driver code from the probe:
> >        struct dma_device *p;
> >        p->dst_addr_widths = zdev->chan->bus_width / 8;
> >        p->src_addr_widths = zdev->chan->bus_width / 8;
> 
> Read what I wrote before and read the documentation for these fields.
> They are bitmasks.

I misunderstood the question that you asked yesterday.
Now I got clarified. Will fix it in the next version of the patch...
Thanks for the detailed explanation.

Regards,
Kedar.

> 
> Rob
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body
> of a message to majordomo@vger.kernel.org More majordomo info at
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