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[PATCH 0/4] drop test_thread_flag checks

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  [PATCH 0/4] drop test_thread_flag checks Dmitry Safonov <dsafonov@virtuozzo.com> - 2016-04-14 20:20 +0200
    [PATCH 1/4] x86/events: down with test_thread_flag(TIF_IA32) Dmitry Safonov <dsafonov@virtuozzo.com> - 2016-04-14 20:20 +0200
      Re: [PATCH 1/4] x86/events: down with test_thread_flag(TIF_IA32) Andy Lutomirski <luto@amacapital.net> - 2016-04-14 20:40 +0200
    [PATCH 2/4] x86/intel: down with test_thread_flag(TIF_IA32) Dmitry Safonov <dsafonov@virtuozzo.com> - 2016-04-14 20:20 +0200

#1379189 — [PATCH 0/4] drop test_thread_flag checks

As it was suggested by Andy, I'm working on TIF_IA32 flag
removal. In this first four places, it's quite trivial to
use user_64bit_mode instead of test_thread_flag().
This should fix possible problems for native applications
that change their code selector to __USER32_CS, but do
not have TIF_IA32 flag.

I still quite don't know what to do with uprobes using
ia32_compat check and will make the next patches about
ptrace & signals usage of TIF_IA32.

Dmitry Safonov (4):
  x86/events: down with test_thread_flag(TIF_IA32)
  x86/intel: down with test_thread_flag(TIF_IA32)
  x86/intel lbr: down with test_thread_flag(TIF_IA32)
  x86/oprofile: down with test_thread_flag(TIF_IA32)

 arch/x86/events/core.c        |  2 +-
 arch/x86/events/intel/core.c  |  2 +-
 arch/x86/events/intel/ds.c    |  2 +-
 arch/x86/events/intel/lbr.c   | 17 ++++++++++-------
 arch/x86/events/perf_event.h  |  2 +-
 arch/x86/oprofile/backtrace.c |  2 +-
 6 files changed, 15 insertions(+), 12 deletions(-)

-- 
2.8.0

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#1379190 — [PATCH 1/4] x86/events: down with test_thread_flag(TIF_IA32)

We can use user_64bit_mode(regs) here instead of thread flag
because we have full register frame.

Signed-off-by: Dmitry Safonov <dsafonov@virtuozzo.com>
---
 arch/x86/events/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 041e442a3e28..91d101a9a6e9 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2269,7 +2269,7 @@ perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
 	struct stack_frame_ia32 frame;
 	const void __user *fp;
 
-	if (!test_thread_flag(TIF_IA32))
+	if (user_64bit_mode(regs))
 		return 0;
 
 	cs_base = get_segment_base(regs->cs);
-- 
2.8.0

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#1379206 — Re: [PATCH 1/4] x86/events: down with test_thread_flag(TIF_IA32)

On Thu, Apr 14, 2016 at 11:10 AM, Dmitry Safonov <dsafonov@virtuozzo.com> wrote:
> We can use user_64bit_mode(regs) here instead of thread flag
> because we have full register frame.
>
> Signed-off-by: Dmitry Safonov <dsafonov@virtuozzo.com>
> ---
>  arch/x86/events/core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index 041e442a3e28..91d101a9a6e9 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -2269,7 +2269,7 @@ perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
>         struct stack_frame_ia32 frame;
>         const void __user *fp;
>
> -       if (!test_thread_flag(TIF_IA32))
> +       if (user_64bit_mode(regs))
>                 return 0;

Peter, I got lost in the code that calls this.  Are regs coming from
the overflow interrupt's regs, current_pt_regs(), or
perf_get_regs_user?

If it's the perf_get_regs_user, then this should be okay, but passing
in the ABI field directly would be even nicer.  If they're coming from
the overflow interrupt's regs or current_pt_regs(), could we change
that?

It might also be nice to make sure that we call perf_get_regs_user
exactly once per overflow interrupt -- i.e. we could push it into the
main code rather than the regs sampling code.

>
>         cs_base = get_segment_base(regs->cs);
> --
> 2.8.0
>



-- 
Andy Lutomirski
AMA Capital Management, LLC

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#1379191 — [PATCH 2/4] x86/intel: down with test_thread_flag(TIF_IA32)

For IP + one insturction fixup there is need to know
in which state (compat/native) is application. Now
it's done with TIF_IA32 test, which is buggy, as
the process may change it's CS register to __USER32_CS
descriptor (and vice-versa) so instruction interpreter
will fail to correctly fixup IP.
Changing to user_64bit_mode to check for interrupt
register set is better, however it may race with task,
that changes it's code selector frequiently.

Signed-off-by: Dmitry Safonov <dsafonov@virtuozzo.com>
---
 arch/x86/events/intel/ds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 8584b90d8e0b..e903a8d3b4b0 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -962,7 +962,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 		old_to = to;
 
 #ifdef CONFIG_X86_64
-		is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
+		is_64bit = kernel_ip(to) || user_64bit_mode(regs);
 #endif
 		insn_init(&insn, kaddr, size, is_64bit);
 		insn_get_length(&insn);
-- 
2.8.0

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