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Re: [PATCH v3 3/7] arm64: Add helpers for detecting AArch32 support at EL0

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  Re: [PATCH v3 3/7] arm64: Add helpers for detecting AArch32 support  at EL0 Will Deacon <will.deacon@arm.com> - 2016-04-14 18:40 +0200
    Re: [PATCH v3 3/7] arm64: Add helpers for detecting AArch32 support  at EL0 Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2016-04-14 18:50 +0200
      Re: [PATCH v3 3/7] arm64: Add helpers for detecting AArch32 support  at EL0 Will Deacon <will.deacon@arm.com> - 2016-04-14 18:50 +0200

#1379076 — Re: [PATCH v3 3/7] arm64: Add helpers for detecting AArch32 support at EL0

On Thu, Mar 31, 2016 at 06:27:31PM +0100, Suzuki K Poulose wrote:
> Adds a helper to extract the support for AArch32 at EL0
> 
> Tested-by: Yury Norov <ynorov@caviumnetworks.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  arch/arm64/include/asm/cpufeature.h |    7 +++++++
>  arch/arm64/include/asm/sysreg.h     |    1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index b9b6494..7f64285 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -170,6 +170,13 @@ static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
>  		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
>  }
>  
> +static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
> +{
> +	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
> +
> +	return val == ID_AA64PFR0_EL0_32BIT_64BIT;

Should this be >=? What are the rules for this register?

Will

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#1379090

On 14/04/16 17:39, Will Deacon wrote:
> On Thu, Mar 31, 2016 at 06:27:31PM +0100, Suzuki K Poulose wrote:
>> Adds a helper to extract the support for AArch32 at EL0
>>
>> Tested-by: Yury Norov <ynorov@caviumnetworks.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>

>> +static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
>> +{
>> +	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
>> +
>> +	return val == ID_AA64PFR0_EL0_32BIT_64BIT;
>
> Should this be >=? What are the rules for this register?

This feature value is kind of "FTR_EXACT" where, we don't know what the relationship
of the values are. Here is the list of possible values :

0001	EL0 can be executed in AArch64 state only.
0010	EL0 can be executed in either AArch64 or AArch32 state.

All the other values are reserved. So I believe "==" is better check.

Suzuki

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#1379093

On Thu, Apr 14, 2016 at 05:46:08PM +0100, Suzuki K Poulose wrote:
> On 14/04/16 17:39, Will Deacon wrote:
> >On Thu, Mar 31, 2016 at 06:27:31PM +0100, Suzuki K Poulose wrote:
> >>Adds a helper to extract the support for AArch32 at EL0
> >>
> >>Tested-by: Yury Norov <ynorov@caviumnetworks.com>
> >>Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> >>+static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
> >>+{
> >>+	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
> >>+
> >>+	return val == ID_AA64PFR0_EL0_32BIT_64BIT;
> >
> >Should this be >=? What are the rules for this register?
> 
> This feature value is kind of "FTR_EXACT" where, we don't know what the relationship
> of the values are. Here is the list of possible values :
> 
> 0001	EL0 can be executed in AArch64 state only.
> 0010	EL0 can be executed in either AArch64 or AArch32 state.
> 
> All the other values are reserved. So I believe "==" is better check.

Yeah, and thinking about it some more, that makes sense. Thanks.

Will

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