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[alsa-devel] [RFC PATCH 0/4] ASoC: Mediatek: Add support for MT2701 SOC

Started byGarlic Tseng <garlic.tseng@mediatek.com>
First post2016-04-14 09:40 +0200
Last post2016-04-14 09:40 +0200
Articles 2 — 1 participant

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  [alsa-devel] [RFC PATCH 0/4] ASoC: Mediatek: Add support for MT2701 SOC Garlic Tseng <garlic.tseng@mediatek.com> - 2016-04-14 09:40 +0200
    [alsa-devel] [RFC PATCH 2/4] ASoC: mediatek: add documents for mt2701 Garlic Tseng <garlic.tseng@mediatek.com> - 2016-04-14 09:40 +0200

#1378552 — [alsa-devel] [RFC PATCH 0/4] ASoC: Mediatek: Add support for MT2701 SOC

FromGarlic Tseng <garlic.tseng@mediatek.com>
Date2016-04-14 09:40 +0200
Subject[alsa-devel] [RFC PATCH 0/4] ASoC: Mediatek: Add support for MT2701 SOC
Message-ID<rnK2C-6Al-7@gated-at.bofh.it>
This patch adds basic support for Mediatek AFE for MT2701 SoC.
The patch is based on broonie tree "for-next" branch.

The interface to connect with BT chip is not finish yet, but as an upstream
rookie I really need some comments. Any comments will be greatly appreciated.

Garlic Tseng (4):
  ASoC: mediatek: Refine mt8173 driver
  ASoC: mediatek: add documents for mt2701
  ASoC: mediatek: add mt2701 platform driver implementation.
  ASoC: mediatek: Add mt2701-cs42448 driver and config option.

 .../devicetree/bindings/sound/mt2701-cs42448.txt   |   39 +
 .../devicetree/bindings/sound/mtk2701-afe-pcm.txt  |  150 ++
 sound/soc/mediatek/Kconfig                         |   21 +
 sound/soc/mediatek/Makefile                        |   15 +-
 sound/soc/mediatek/mt2701/Makefile                 |   20 +
 sound/soc/mediatek/mt2701/mt2701-cs42448.c         |  376 +++++
 sound/soc/mediatek/mt2701/mtk2701-afe-clock-ctrl.c |  259 +++
 sound/soc/mediatek/mt2701/mtk2701-afe-clock-ctrl.h |   28 +
 sound/soc/mediatek/mt2701/mtk2701-afe-common.h     |  217 +++
 sound/soc/mediatek/mt2701/mtk2701-afe-pcm.c        | 1752 ++++++++++++++++++++
 sound/soc/mediatek/mt2701/mtk2701-irq.c            |  109 ++
 sound/soc/mediatek/mt2701/mtk2701-irq.h            |   30 +
 sound/soc/mediatek/mt2701/mtk2701-reg.h            |  165 ++
 sound/soc/mediatek/mt8173-max98090.c               |  213 ---
 sound/soc/mediatek/mt8173-rt5650-rt5514.c          |  258 ---
 sound/soc/mediatek/mt8173-rt5650-rt5676.c          |  288 ----
 sound/soc/mediatek/mt8173-rt5650.c                 |  236 ---
 sound/soc/mediatek/mt8173/Makefile                 |    7 +
 sound/soc/mediatek/mt8173/mt8173-max98090.c        |  213 +++
 sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c   |  258 +++
 sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c   |  288 ++++
 sound/soc/mediatek/mt8173/mt8173-rt5650.c          |  236 +++
 sound/soc/mediatek/mt8173/mtk-afe-common.h         |  101 ++
 sound/soc/mediatek/mt8173/mtk-afe-pcm.c            | 1333 +++++++++++++++
 sound/soc/mediatek/mtk-afe-common.h                |  101 --
 sound/soc/mediatek/mtk-afe-pcm.c                   | 1333 ---------------
 26 files changed, 5610 insertions(+), 2436 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/mt2701-cs42448.txt
 create mode 100644 Documentation/devicetree/bindings/sound/mtk2701-afe-pcm.txt
 create mode 100644 sound/soc/mediatek/mt2701/Makefile
 create mode 100644 sound/soc/mediatek/mt2701/mt2701-cs42448.c
 create mode 100644 sound/soc/mediatek/mt2701/mtk2701-afe-clock-ctrl.c
 create mode 100644 sound/soc/mediatek/mt2701/mtk2701-afe-clock-ctrl.h
 create mode 100644 sound/soc/mediatek/mt2701/mtk2701-afe-common.h
 create mode 100644 sound/soc/mediatek/mt2701/mtk2701-afe-pcm.c
 create mode 100644 sound/soc/mediatek/mt2701/mtk2701-irq.c
 create mode 100644 sound/soc/mediatek/mt2701/mtk2701-irq.h
 create mode 100644 sound/soc/mediatek/mt2701/mtk2701-reg.h
 delete mode 100644 sound/soc/mediatek/mt8173-max98090.c
 delete mode 100644 sound/soc/mediatek/mt8173-rt5650-rt5514.c
 delete mode 100644 sound/soc/mediatek/mt8173-rt5650-rt5676.c
 delete mode 100644 sound/soc/mediatek/mt8173-rt5650.c
 create mode 100644 sound/soc/mediatek/mt8173/Makefile
 create mode 100644 sound/soc/mediatek/mt8173/mt8173-max98090.c
 create mode 100644 sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
 create mode 100644 sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
 create mode 100644 sound/soc/mediatek/mt8173/mt8173-rt5650.c
 create mode 100644 sound/soc/mediatek/mt8173/mtk-afe-common.h
 create mode 100644 sound/soc/mediatek/mt8173/mtk-afe-pcm.c
 delete mode 100644 sound/soc/mediatek/mtk-afe-common.h
 delete mode 100644 sound/soc/mediatek/mtk-afe-pcm.c

-- 
1.9.1

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#1378555 — [alsa-devel] [RFC PATCH 2/4] ASoC: mediatek: add documents for mt2701

FromGarlic Tseng <garlic.tseng@mediatek.com>
Date2016-04-14 09:40 +0200
Subject[alsa-devel] [RFC PATCH 2/4] ASoC: mediatek: add documents for mt2701
Message-ID<rnK2D-6Al-35@gated-at.bofh.it>
In reply to#1378552
Add documents for mt2701-cs42448 machine driver and mt2701 platform driver.

Signed-off-by: Garlic Tseng <garlic.tseng@mediatek.com>
---
 .../devicetree/bindings/sound/mt2701-cs42448.txt   |  39 ++++++
 .../devicetree/bindings/sound/mtk2701-afe-pcm.txt  | 150 +++++++++++++++++++++
 2 files changed, 189 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/mt2701-cs42448.txt
 create mode 100644 Documentation/devicetree/bindings/sound/mtk2701-afe-pcm.txt

diff --git a/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt b/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt
new file mode 100644
index 0000000..be5d9b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt
@@ -0,0 +1,39 @@
+MT2701 with CS42448 CODEC
+
+Required properties:
+- compatible : "mediatek,mt2701-cs42448-machin"
+- mediatek,platform: the phandle of MT8173 ASoC platform
+- audio-routing: a list of the connections between audio
+- pinctrl-names: Should contain only one value - "default"
+- pinctrl-0: Should specify pin control groups used for this controller.
+- i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to
+					control I2S1-in mux.
+
+Example:
+
+	sound:sound {
+		compatible = "mediatek,mt2701-cs42448-machine";
+		mediatek,platform = <&afe>;
+		/* CS42448 Machine name */
+		audio-routing =
+			"Line Out Jack", "AOUT1L",
+			"Line Out Jack", "AOUT1R",
+			"Line Out Jack", "AOUT2L",
+			"Line Out Jack", "AOUT2R",
+			"Line Out Jack", "AOUT3L",
+			"Line Out Jack", "AOUT3R",
+			"Line Out Jack", "AOUT4L",
+			"Line Out Jack", "AOUT4R",
+			"AIN1L", "AMIC",
+			"AIN1R", "AMIC",
+			"AIN2L", "Tuner In",
+			"AIN2R", "Tuner In",
+			"AIN3L", "Satellite Tuner In",
+			"AIN3R", "Satellite Tuner In",
+			"AIN3L", "AUX In",
+			"AIN3R", "AUX In";
+		pinctrl-names = "default";
+		pinctrl-0 = <&aud_pins_default>;
+		i2s1-in-sel-gpio1 = <&pio 53 0>;
+		i2s1-in-sel-gpio2 = <&pio 54 0>;
+	};
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/sound/mtk2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mtk2701-afe-pcm.txt
new file mode 100644
index 0000000..02232ca0
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mtk2701-afe-pcm.txt
@@ -0,0 +1,150 @@
+Mediatek AFE PCM controller for mt2701
+
+Required properties:
+- compatible = "mediatek,mt2701-audio";
+- reg: register location and size
+- interrupts: Should contain AFE interrupt
+- clock-names: should have these clock names:
+		"infra_sys_audio_clk",
+		"top_audio_mux1_sel",
+		"top_audio_mux2_sel",
+		"top_audio_mux1_div",
+		"top_audio_mux2_div",
+		"top_audio_48k_timing",
+		"top_audio_44k_timing",
+		"top_audpll_mux_sel",
+		"top_apll_sel",
+		"top_aud1_pll_98M",
+		"top_aud2_pll_90M",
+		"top_hadds2_pll_98M",
+		"top_hadds2_pll_294M",
+		"top_audpll",
+		"top_audpll_d4",
+		"top_audpll_d8",
+		"top_audpll_d16",
+		"top_audpll_d24",
+		"top_audintbus_sel",
+		"clk_26m",
+		"top_syspll1_d4",
+		"top_aud_k1_src_sel",
+		"top_aud_k2_src_sel",
+		"top_aud_k3_src_sel",
+		"top_aud_k4_src_sel",
+		"top_aud_k5_src_sel",
+		"top_aud_k6_src_sel",
+		"top_aud_k1_src_div",
+		"top_aud_k2_src_div",
+		"top_aud_k3_src_div",
+		"top_aud_k4_src_div",
+		"top_aud_k5_src_div",
+		"top_aud_k6_src_div",
+		"top_aud_i2s1_mclk",
+		"top_aud_i2s2_mclk",
+		"top_aud_i2s3_mclk",
+		"top_aud_i2s4_mclk",
+		"top_aud_i2s5_mclk",
+		"top_aud_i2s6_mclk",
+		"top_asm_m_sel",
+		"top_asm_h_sel",
+		"top_univpll2_d4",
+		"top_univpll2_d2",
+		"top_syspll_d5";
+
+Example:
+
+	afe: mt8173-afe-pcm@11220000 {
+		compatible = "mediatek,mt2701-audio";
+		reg = <0 0x11220000 0 0x2000>,
+		      <0 0x112A0000 0 0x20000>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_AUDIO>,
+			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
+			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
+			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
+			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
+			 <&topckgen CLK_TOP_APLL_SEL>,
+			 <&topckgen CLK_TOP_AUD1PLL_98M>,
+			 <&topckgen CLK_TOP_AUD2PLL_90M>,
+			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
+			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
+			 <&topckgen CLK_TOP_AUDPLL>,
+			 <&topckgen CLK_TOP_AUDPLL_D4>,
+			 <&topckgen CLK_TOP_AUDPLL_D8>,
+			 <&topckgen CLK_TOP_AUDPLL_D16>,
+			 <&topckgen CLK_TOP_AUDPLL_D24>,
+			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
+			 <&clk26m>,
+			 <&topckgen CLK_TOP_SYSPLL1_D4>,
+			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
+			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
+			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
+			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
+			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
+			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
+			 <&topckgen CLK_TOP_ASM_M_SEL>,
+			 <&topckgen CLK_TOP_ASM_H_SEL>,
+			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
+			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
+			 <&topckgen CLK_TOP_SYSPLL_D5>;
+
+		clock-names = "infra_sys_audio_clk",
+			      "top_audio_mux1_sel",
+			      "top_audio_mux2_sel",
+			      "top_audio_mux1_div",
+			      "top_audio_mux2_div",
+			      "top_audio_48k_timing",
+			      "top_audio_44k_timing",
+			      "top_audpll_mux_sel",
+			      "top_apll_sel",
+			      "top_aud1_pll_98M",
+			      "top_aud2_pll_90M",
+			      "top_hadds2_pll_98M",
+			      "top_hadds2_pll_294M",
+			      "top_audpll",
+			      "top_audpll_d4",
+			      "top_audpll_d8",
+			      "top_audpll_d16",
+			      "top_audpll_d24",
+			      "top_audintbus_sel",
+			      "clk_26m",
+			      "top_syspll1_d4",
+			      "top_aud_k1_src_sel",
+			      "top_aud_k2_src_sel",
+			      "top_aud_k3_src_sel",
+			      "top_aud_k4_src_sel",
+			      "top_aud_k5_src_sel",
+			      "top_aud_k6_src_sel",
+			      "top_aud_k1_src_div",
+			      "top_aud_k2_src_div",
+			      "top_aud_k3_src_div",
+			      "top_aud_k4_src_div",
+			      "top_aud_k5_src_div",
+			      "top_aud_k6_src_div",
+			      "top_aud_i2s1_mclk",
+			      "top_aud_i2s2_mclk",
+			      "top_aud_i2s3_mclk",
+			      "top_aud_i2s4_mclk",
+			      "top_aud_i2s5_mclk",
+			      "top_aud_i2s6_mclk",
+			      "top_asm_m_sel",
+			      "top_asm_h_sel",
+			      "top_univpll2_d4",
+			      "top_univpll2_d2",
+			      "top_syspll_d5";
+	};
-- 
1.9.1

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