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[PATCH v9 08/20] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line

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  [PATCH v9 08/20] PM / devfreq: exynos: Add the detailed correlation  between sub-blocks and power line Chanwoo Choi <cw00.choi@samsung.com> - 2016-04-11 06:00 +0200
    Re: [PATCH v9 08/20] PM / devfreq: exynos: Add the detailed  correlation between sub-blocks and power line Chanwoo Choi <cw00.choi@samsung.com> - 2016-04-12 10:30 +0200

#1375456 — [PATCH v9 08/20] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line

This patch adds the detailed corrleation between sub-blocks and power line
for Exynos3250, Exynos4210 and Exynos4x12.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
---
 .../devicetree/bindings/devfreq/exynos-bus.txt     | 51 ++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index 03f13d38f1a1..b098fa2ba5d4 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -53,6 +53,57 @@ Optional properties only for parent bus device:
 - exynos,voltage-tolerance: the percentage value for bus voltage tolerance
 			which is used to calculate the max voltage.
 
+Detailed correlation between sub-blocks and power line according to Exynos SoC:
+- In case of Exynos3250, there are two power line as following:
+	VDD_MIF |--- DMC
+
+	VDD_INT |--- LEFTBUS (parent device)
+		|--- PERIL
+		|--- MFC
+		|--- G3D
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- FSYS
+		|--- LCD0
+		|--- PERIR
+		|--- ISP
+		|--- CAM
+
+- In case of Exynos4210, there is one power line as following:
+	VDD_INT |--- DMC (parent device)
+		|--- LEFTBUS
+		|--- PERIL
+		|--- MFC(L)
+		|--- G3D
+		|--- TV
+		|--- LCD0
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- MFC(R)
+		|--- CAM
+		|--- FSYS
+		|--- GPS
+		|--- LCD0
+		|--- LCD1
+
+- In case of Exynos4x12, there are two power line as following:
+	VDD_MIF |--- DMC
+
+	VDD_INT |--- LEFTBUS (parent device)
+		|--- PERIL
+		|--- MFC(L)
+		|--- G3D
+		|--- TV
+		|--- IMAGE
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- MFC(R)
+		|--- CAM
+		|--- FSYS
+		|--- GPS
+		|--- LCD0
+		|--- ISP
+
 Example1:
 	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 	power line (regulator). The MIF (Memory Interface) AXI bus is used to
-- 
1.9.1

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#1376552 — Re: [PATCH v9 08/20] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line

On 2016년 04월 12일 16:35, Krzysztof Kozlowski wrote:
> On 04/11/2016 05:57 AM, Chanwoo Choi wrote:
>> This patch adds the detailed corrleation between sub-blocks and power line
> 
> s/corrleation/correlation/

OK. I'll fix it.

> 
> 
>> for Exynos3250, Exynos4210 and Exynos4x12.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
>> ---
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 51 ++++++++++++++++++++++
>>  1 file changed, 51 insertions(+)
> 
> 
> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> 

Best Regards,
Chanwoo Choi

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