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Groups > linux.kernel > #1371026 > unrolled thread
| Started by | Tai Tri Nguyen <ttnguyen@apm.com> |
|---|---|
| First post | 2016-04-05 01:50 +0200 |
| Last post | 2016-04-06 00:00 +0200 |
| Articles | 5 — 2 participants |
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Re: [PATCH 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Tai Tri Nguyen <ttnguyen@apm.com> - 2016-04-05 01:50 +0200
Re: [PATCH 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Mark Rutland <mark.rutland@arm.com> - 2016-04-05 04:30 +0200
Re: [PATCH 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Tai Tri Nguyen <ttnguyen@apm.com> - 2016-04-05 21:00 +0200
Re: [PATCH 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Mark Rutland <mark.rutland@arm.com> - 2016-04-05 23:40 +0200
Re: [PATCH 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Tai Tri Nguyen <ttnguyen@apm.com> - 2016-04-06 00:00 +0200
| From | Tai Tri Nguyen <ttnguyen@apm.com> |
|---|---|
| Date | 2016-04-05 01:50 +0200 |
| Subject | Re: [PATCH 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding |
| Message-ID | <rkmpR-2lv-53@gated-at.bofh.it> |
Hi Mark, On Fri, Apr 1, 2016 at 5:30 AM, Mark Rutland <mark.rutland@arm.com> wrote: > Hi, > > As per Documentation/devicetree/bindings/submitting-patches.txt, please > put binding patches earlier in a series than the code using them. > > On Thu, Mar 31, 2016 at 04:37:50PM -0700, Tai Nguyen wrote: >> Documentation: Add documentation for APM X-Gene SoC PMU DTS binding >> >> Signed-off-by: Tai Nguyen <ttnguyen@apm.com> >> --- >> .../devicetree/bindings/perf/apm-xgene-pmu.txt | 116 +++++++++++++++++++++ >> 1 file changed, 116 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt >> >> diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt >> new file mode 100644 >> index 0000000..40dfd4e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt >> @@ -0,0 +1,116 @@ >> +* APM X-Gene SoC PMU bindings >> + >> +This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. >> +The following PMU devices are supported: >> + >> + L3C - L3 cache controller >> + IOB - IO bridge >> + MCB - Memory controller bridge >> + MC - Memory controller > > These sound like separate units. How do these relate? > > Is there an SOC-wide PMU that aggregates counters, or are these actually > independent? > Yes, they are independent, but sharing the same top level status interrupt. There's no SOC-wide PMU which aggregates these counters. >> + >> +The following section describes the SoC PMU DT node binding. >> + >> +Required properties: >> +- compatible : Shall be "apm,xgene-pmu" for revision 1 or >> + "apm,xgene-pmu-v2" for revision 2. > > That name is very general. Is there not a more specific name for the SOC > PMU? > Beside the ARMv8 core PMU which has the compatible name "arm,armv8-pmuv3", these are all the PMUs in X-Gene SoCs. Also, we are using the same PMU driver across our platforms. I think a general name is what it should be. >> +Required properties for L3C subnode: >> +- compatible : Shall be "apm,xgene-pmu-l3c". >> +- reg : First resource shall be the L3C PMU resource. >> +- index : Instance number of the L3C PMU. >> + >> +Required properties for IOB subnode: >> +- compatible : Shall be "apm,xgene-pmu-iob". >> +- reg : First resource shall be the IOB PMU resource. >> +- index : Instance number of the IOB PMU. >> + >> +Required properties for MCB subnode: >> +- compatible : Shall be "apm,xgene-pmu-mcb". >> +- reg : First resource shall be the MCB PMU resource. >> +- index : Instance number of the MCB PMU. >> + >> +Required properties for MC subnode: >> +- compatible : Shall be "apm,xgene-pmu-mc". >> +- reg : First resource shall be the MC PMU resource. >> +- index : Instance number of the MC PMU. > > What's the index property useful for? > The index property is used for indicating the physical hardware PMU id. For example, on X-Gene1 there are 4 memory controllers (MC), each of them has its own PMU. The index property tells us which MC a PMU belongs to. The same for MCB/L3C and IOB. > Thanks, > Mark. Thanks, Tai
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| From | Mark Rutland <mark.rutland@arm.com> |
|---|---|
| Date | 2016-04-05 04:30 +0200 |
| Message-ID | <rkoUH-4m4-25@gated-at.bofh.it> |
| In reply to | #1371026 |
On Mon, Apr 04, 2016 at 04:40:33PM -0700, Tai Tri Nguyen wrote: > On Fri, Apr 1, 2016 at 5:30 AM, Mark Rutland <mark.rutland@arm.com> wrote: > > On Thu, Mar 31, 2016 at 04:37:50PM -0700, Tai Nguyen wrote: > >> +This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. > >> +The following PMU devices are supported: > >> + > >> + L3C - L3 cache controller > >> + IOB - IO bridge > >> + MCB - Memory controller bridge > >> + MC - Memory controller > > > > These sound like separate units. How do these relate? > > > > Is there an SOC-wide PMU that aggregates counters, or are these actually > > independent? > > > > Yes, they are independent, but sharing the same top level status interrupt. > There's no SOC-wide PMU which aggregates these counters. If they're just sharing the interrupt, why are they not separate nodes (and drivers) which simply happen to share an interrupt? Is there anything else shared? > >> +The following section describes the SoC PMU DT node binding. > >> + > >> +Required properties: > >> +- compatible : Shall be "apm,xgene-pmu" for revision 1 or > >> + "apm,xgene-pmu-v2" for revision 2. > > > > That name is very general. Is there not a more specific name for the SOC > > PMU? > > > > Beside the ARMv8 core PMU which has the compatible name "arm,armv8-pmuv3", > these are all the PMUs in X-Gene SoCs. Also, we are using the same PMU > driver across our platforms. I think a general name is what it should be. Depending on my prior question, I'm not sure that's necessarily true. If there's no actual shared SoC PMU logic as such, the names below for each individual PMU seem fine. > >> +Required properties for L3C subnode: > >> +- compatible : Shall be "apm,xgene-pmu-l3c". > >> +- reg : First resource shall be the L3C PMU resource. > >> +- index : Instance number of the L3C PMU. > >> + > >> +Required properties for IOB subnode: > >> +- compatible : Shall be "apm,xgene-pmu-iob". > >> +- reg : First resource shall be the IOB PMU resource. > >> +- index : Instance number of the IOB PMU. > >> + > >> +Required properties for MCB subnode: > >> +- compatible : Shall be "apm,xgene-pmu-mcb". > >> +- reg : First resource shall be the MCB PMU resource. > >> +- index : Instance number of the MCB PMU. > >> + > >> +Required properties for MC subnode: > >> +- compatible : Shall be "apm,xgene-pmu-mc". > >> +- reg : First resource shall be the MC PMU resource. > >> +- index : Instance number of the MC PMU. > > > > What's the index property useful for? > > > > The index property is used for indicating the physical hardware PMU id. > For example, on X-Gene1 there are 4 memory controllers (MC), each of them has > its own PMU. The index property tells us which MC a PMU belongs to. > The same for MCB/L3C and IOB. Sure, but is this simply informative for the user, or does this have an impact on the programming model? Thanks, Mark.
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| From | Tai Tri Nguyen <ttnguyen@apm.com> |
|---|---|
| Date | 2016-04-05 21:00 +0200 |
| Message-ID | <rkEmK-8qt-13@gated-at.bofh.it> |
| In reply to | #1371130 |
Hi Mark, On Mon, Apr 4, 2016 at 4:38 PM, Mark Rutland <mark.rutland@arm.com> wrote: > On Mon, Apr 04, 2016 at 04:40:33PM -0700, Tai Tri Nguyen wrote: >> On Fri, Apr 1, 2016 at 5:30 AM, Mark Rutland <mark.rutland@arm.com> wrote: >> > On Thu, Mar 31, 2016 at 04:37:50PM -0700, Tai Nguyen wrote: >> >> +This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. >> >> +The following PMU devices are supported: >> >> + >> >> + L3C - L3 cache controller >> >> + IOB - IO bridge >> >> + MCB - Memory controller bridge >> >> + MC - Memory controller >> > >> > These sound like separate units. How do these relate? >> > >> > Is there an SOC-wide PMU that aggregates counters, or are these actually >> > independent? >> > >> >> Yes, they are independent, but sharing the same top level status interrupt. >> There's no SOC-wide PMU which aggregates these counters. > > If they're just sharing the interrupt, why are they not separate nodes (and > drivers) which simply happen to share an interrupt? > > Is there anything else shared? Yes, a long with the interrupt they also share top level PMU status CSR region. > >> >> +The following section describes the SoC PMU DT node binding. >> >> + >> >> +Required properties: >> >> +- compatible : Shall be "apm,xgene-pmu" for revision 1 or >> >> + "apm,xgene-pmu-v2" for revision 2. >> > >> > That name is very general. Is there not a more specific name for the SOC >> > PMU? >> > >> >> Beside the ARMv8 core PMU which has the compatible name "arm,armv8-pmuv3", >> these are all the PMUs in X-Gene SoCs. Also, we are using the same PMU >> driver across our platforms. I think a general name is what it should be. > > Depending on my prior question, I'm not sure that's necessarily true. If > there's no actual shared SoC PMU logic as such, the names below for each > individual PMU seem fine. > Given that they are sharing the same top level PMU status CSRs, a combined driver seems to be the best approach in my opinion. >> >> +Required properties for L3C subnode: >> >> +- compatible : Shall be "apm,xgene-pmu-l3c". >> >> +- reg : First resource shall be the L3C PMU resource. >> >> +- index : Instance number of the L3C PMU. >> >> + >> >> +Required properties for IOB subnode: >> >> +- compatible : Shall be "apm,xgene-pmu-iob". >> >> +- reg : First resource shall be the IOB PMU resource. >> >> +- index : Instance number of the IOB PMU. >> >> + >> >> +Required properties for MCB subnode: >> >> +- compatible : Shall be "apm,xgene-pmu-mcb". >> >> +- reg : First resource shall be the MCB PMU resource. >> >> +- index : Instance number of the MCB PMU. >> >> + >> >> +Required properties for MC subnode: >> >> +- compatible : Shall be "apm,xgene-pmu-mc". >> >> +- reg : First resource shall be the MC PMU resource. >> >> +- index : Instance number of the MC PMU. >> > >> > What's the index property useful for? >> > >> >> The index property is used for indicating the physical hardware PMU id. >> For example, on X-Gene1 there are 4 memory controllers (MC), each of them has >> its own PMU. The index property tells us which MC a PMU belongs to. >> The same for MCB/L3C and IOB. > > Sure, but is this simply informative for the user, or does this have an impact > on the programming model? > Yes, it does impact. For example, there are 4 PMUs associated with 4 MCs. They all certainly have the same sort of events. The index will help to determine the right event users want to monitor. Below is an example of perf list output: ... mc0/mcu-rd-request/ ... mc1/mcu-rd-request/ ... Regards, -- Tai
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| From | Mark Rutland <mark.rutland@arm.com> |
|---|---|
| Date | 2016-04-05 23:40 +0200 |
| Message-ID | <rkGRA-1Og-13@gated-at.bofh.it> |
| In reply to | #1371892 |
On Tue, Apr 05, 2016 at 11:51:02AM -0700, Tai Tri Nguyen wrote: > Hi Mark, > > On Mon, Apr 4, 2016 at 4:38 PM, Mark Rutland <mark.rutland@arm.com> wrote: > > On Mon, Apr 04, 2016 at 04:40:33PM -0700, Tai Tri Nguyen wrote: > >> On Fri, Apr 1, 2016 at 5:30 AM, Mark Rutland <mark.rutland@arm.com> wrote: > >> > On Thu, Mar 31, 2016 at 04:37:50PM -0700, Tai Nguyen wrote: > >> >> +This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. > >> >> +The following PMU devices are supported: > >> >> + > >> >> + L3C - L3 cache controller > >> >> + IOB - IO bridge > >> >> + MCB - Memory controller bridge > >> >> + MC - Memory controller > >> > > >> > These sound like separate units. How do these relate? > >> > > >> > Is there an SOC-wide PMU that aggregates counters, or are these actually > >> > independent? > >> > > >> > >> Yes, they are independent, but sharing the same top level status interrupt. > >> There's no SOC-wide PMU which aggregates these counters. > > > > If they're just sharing the interrupt, why are they not separate nodes (and > > drivers) which simply happen to share an interrupt? > > > > Is there anything else shared? > > Yes, a long with the interrupt they also share top level PMU status CSR region. Ah, ok. I had missed that. What exactly exists in that region? Are the shared registers just for handling the shared interrupt, or are they used to handle other parts of the PMUs too? > >> >> +Required properties for L3C subnode: > >> >> +- compatible : Shall be "apm,xgene-pmu-l3c". > >> >> +- reg : First resource shall be the L3C PMU resource. > >> >> +- index : Instance number of the L3C PMU. > >> >> + > >> >> +Required properties for IOB subnode: > >> >> +- compatible : Shall be "apm,xgene-pmu-iob". > >> >> +- reg : First resource shall be the IOB PMU resource. > >> >> +- index : Instance number of the IOB PMU. > >> >> + > >> >> +Required properties for MCB subnode: > >> >> +- compatible : Shall be "apm,xgene-pmu-mcb". > >> >> +- reg : First resource shall be the MCB PMU resource. > >> >> +- index : Instance number of the MCB PMU. > >> >> + > >> >> +Required properties for MC subnode: > >> >> +- compatible : Shall be "apm,xgene-pmu-mc". > >> >> +- reg : First resource shall be the MC PMU resource. > >> >> +- index : Instance number of the MC PMU. > >> > > >> > What's the index property useful for? > >> > > >> > >> The index property is used for indicating the physical hardware PMU id. > >> For example, on X-Gene1 there are 4 memory controllers (MC), each of them has > >> its own PMU. The index property tells us which MC a PMU belongs to. > >> The same for MCB/L3C and IOB. > > > > Sure, but is this simply informative for the user, or does this have an impact > > on the programming model? > > > > Yes, it does impact. For example, there are 4 PMUs associated with 4 MCs. > They all certainly have the same sort of events. The index will help > to determine > the right event users want to monitor. Below is an example of perf list output: > ... > mc0/mcu-rd-request/ > ... > mc1/mcu-rd-request/ By "programming model" I mean the way the kernel interacts with the device, rather than the interface exposed to userspace. For example, does the index affect which bits are used in the shared CSR region? If it's only used for the name exposed to userspace, that's fine. Otherwise, there may be subtle gotchas. Thanks, Mark.
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| From | Tai Tri Nguyen <ttnguyen@apm.com> |
|---|---|
| Date | 2016-04-06 00:00 +0200 |
| Message-ID | <rkHaW-1X2-5@gated-at.bofh.it> |
| In reply to | #1371970 |
Hi Mark, On Tue, Apr 5, 2016 at 12:31 PM, Mark Rutland <mark.rutland@arm.com> wrote: > On Tue, Apr 05, 2016 at 11:51:02AM -0700, Tai Tri Nguyen wrote: >> Hi Mark, >> >> On Mon, Apr 4, 2016 at 4:38 PM, Mark Rutland <mark.rutland@arm.com> wrote: >> > On Mon, Apr 04, 2016 at 04:40:33PM -0700, Tai Tri Nguyen wrote: >> >> On Fri, Apr 1, 2016 at 5:30 AM, Mark Rutland <mark.rutland@arm.com> wrote: >> >> > On Thu, Mar 31, 2016 at 04:37:50PM -0700, Tai Nguyen wrote: >> >> >> +This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. >> >> >> +The following PMU devices are supported: >> >> >> + >> >> >> + L3C - L3 cache controller >> >> >> + IOB - IO bridge >> >> >> + MCB - Memory controller bridge >> >> >> + MC - Memory controller >> >> > >> >> > These sound like separate units. How do these relate? >> >> > >> >> > Is there an SOC-wide PMU that aggregates counters, or are these actually >> >> > independent? >> >> > >> >> >> >> Yes, they are independent, but sharing the same top level status interrupt. >> >> There's no SOC-wide PMU which aggregates these counters. >> > >> > If they're just sharing the interrupt, why are they not separate nodes (and >> > drivers) which simply happen to share an interrupt? >> > >> > Is there anything else shared? >> >> Yes, a long with the interrupt they also share top level PMU status CSR region. > > Ah, ok. I had missed that. > > What exactly exists in that region? Are the shared registers just for handling > the shared interrupt, or are they used to handle other parts of the PMUs too? They are shared registers for handling the shared interrupt only, indicating/masking source of the shared interrupt. > >> >> >> +Required properties for L3C subnode: >> >> >> +- compatible : Shall be "apm,xgene-pmu-l3c". >> >> >> +- reg : First resource shall be the L3C PMU resource. >> >> >> +- index : Instance number of the L3C PMU. >> >> >> + >> >> >> +Required properties for IOB subnode: >> >> >> +- compatible : Shall be "apm,xgene-pmu-iob". >> >> >> +- reg : First resource shall be the IOB PMU resource. >> >> >> +- index : Instance number of the IOB PMU. >> >> >> + >> >> >> +Required properties for MCB subnode: >> >> >> +- compatible : Shall be "apm,xgene-pmu-mcb". >> >> >> +- reg : First resource shall be the MCB PMU resource. >> >> >> +- index : Instance number of the MCB PMU. >> >> >> + >> >> >> +Required properties for MC subnode: >> >> >> +- compatible : Shall be "apm,xgene-pmu-mc". >> >> >> +- reg : First resource shall be the MC PMU resource. >> >> >> +- index : Instance number of the MC PMU. >> >> > >> >> > What's the index property useful for? >> >> > >> >> >> >> The index property is used for indicating the physical hardware PMU id. >> >> For example, on X-Gene1 there are 4 memory controllers (MC), each of them has >> >> its own PMU. The index property tells us which MC a PMU belongs to. >> >> The same for MCB/L3C and IOB. >> > >> > Sure, but is this simply informative for the user, or does this have an impact >> > on the programming model? >> > >> >> Yes, it does impact. For example, there are 4 PMUs associated with 4 MCs. >> They all certainly have the same sort of events. The index will help >> to determine >> the right event users want to monitor. Below is an example of perf list output: >> ... >> mc0/mcu-rd-request/ >> ... >> mc1/mcu-rd-request/ > > By "programming model" I mean the way the kernel interacts with the device, > rather than the interface exposed to userspace. For example, does the index > affect which bits are used in the shared CSR region? > > If it's only used for the name exposed to userspace, that's fine. > > Otherwise, there may be subtle gotchas. No, it doesn't impact in that mean. Regards, -- Tai
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