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Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

Started byTony Lindgren <tony@atomide.com>
First post2016-03-30 23:20 +0200
Last post2016-04-01 21:10 +0200
Articles 8 — 3 participants

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  Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Tony Lindgren <tony@atomide.com> - 2016-03-30 23:20 +0200
    Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Tony Lindgren <tony@atomide.com> - 2016-03-30 23:40 +0200
      Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Tero Kristo <t-kristo@ti.com> - 2016-03-31 08:40 +0200
        Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Keerthy <a0393675@ti.com> - 2016-03-31 11:30 +0200
          Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Tony Lindgren <tony@atomide.com> - 2016-03-31 19:10 +0200
            Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Tony Lindgren <tony@atomide.com> - 2016-04-01 17:40 +0200
              Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Tero Kristo <t-kristo@ti.com> - 2016-04-01 20:50 +0200
                Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck Tony Lindgren <tony@atomide.com> - 2016-04-01 21:10 +0200

#1367615 — Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

FromTony Lindgren <tony@atomide.com>
Date2016-03-30 23:20 +0200
SubjectRe: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck
Message-ID<rivGV-2PT-1@gated-at.bofh.it>
* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> crystal is not enabled at power up. Instead the CPU falls back to using
> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)

Thanks applying into omap-for-v4.6/fixes.

Tony

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#1367625

FromTony Lindgren <tony@atomide.com>
Date2016-03-30 23:40 +0200
Message-ID<riw0h-2Yu-3@gated-at.bofh.it>
In reply to#1367615
* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
> > This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> > crystal is not enabled at power up. Instead the CPU falls back to using
> > an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> > 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> 
> Thanks applying into omap-for-v4.6/fixes.

Actually let's wait a review from Tero on this one, not sure
about the pseudo clock naming here. So dropping for now.

Regards,

Tony

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#1367851

FromTero Kristo <t-kristo@ti.com>
Date2016-03-31 08:40 +0200
Message-ID<riEqS-P8-15@gated-at.bofh.it>
In reply to#1367625
On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>
>> Thanks applying into omap-for-v4.6/fixes.
>
> Actually let's wait a review from Tero on this one, not sure
> about the pseudo clock naming here. So dropping for now.

The patch is fine for me, I didn't comment anything before as I thought 
you already applied it.

Acked-by: Tero Kristo <t-kristo@ti.com>

>
> Regards,
>
> Tony
>

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#1368066

FromKeerthy <a0393675@ti.com>
Date2016-03-31 11:30 +0200
Message-ID<riH5o-2PS-23@gated-at.bofh.it>
In reply to#1367851

On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>> external
>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>> usually
>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>
>>> Thanks applying into omap-for-v4.6/fixes.
>>
>> Actually let's wait a review from Tero on this one, not sure
>> about the pseudo clock naming here. So dropping for now.
>
> The patch is fine for me, I didn't comment anything before as I thought
> you already applied it.
>
> Acked-by: Tero Kristo <t-kristo@ti.com>

Thanks Tero.

>
>>
>> Regards,
>>
>> Tony
>>
>

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#1368457

FromTony Lindgren <tony@atomide.com>
Date2016-03-31 19:10 +0200
Message-ID<riOgy-8hI-23@gated-at.bofh.it>
In reply to#1368066
* Keerthy <a0393675@ti.com> [160331 02:26]:
> 
> 
> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> >>* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> >>>* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> >>>>external
> >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> >>>>usually
> >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> >>>
> >>>Thanks applying into omap-for-v4.6/fixes.
> >>
> >>Actually let's wait a review from Tero on this one, not sure
> >>about the pseudo clock naming here. So dropping for now.
> >
> >The patch is fine for me, I didn't comment anything before as I thought
> >you already applied it.
> >
> >Acked-by: Tero Kristo <t-kristo@ti.com>
> 
> Thanks Tero.

OK applying with Tero's ack.

Tony

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#1369428

FromTony Lindgren <tony@atomide.com>
Date2016-04-01 17:40 +0200
Message-ID<rj9l0-6nD-21@gated-at.bofh.it>
In reply to#1368457
Hi,

* Tony Lindgren <tony@atomide.com> [160331 10:04]:
> * Keerthy <a0393675@ti.com> [160331 02:26]:
> > 
> > 
> > On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> > >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> > >>* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> > >>>* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> > >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> > >>>>external
> > >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> > >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> > >>>>usually
> > >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> > >>>
> > >>>Thanks applying into omap-for-v4.6/fixes.
> > >>
> > >>Actually let's wait a review from Tero on this one, not sure
> > >>about the pseudo clock naming here. So dropping for now.
> > >
> > >The patch is fine for me, I didn't comment anything before as I thought
> > >you already applied it.
> > >
> > >Acked-by: Tero Kristo <t-kristo@ti.com>
> > 
> > Thanks Tero.
> 
> OK applying with Tero's ack.

I'm dropping this again as it introduces new warnings with make dtbs:

Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra7-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra72-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck

Regards,

Tony

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#1369528

FromTero Kristo <t-kristo@ti.com>
Date2016-04-01 20:50 +0200
Message-ID<rjciS-8u7-23@gated-at.bofh.it>
In reply to#1369428
On 04/01/2016 06:36 PM, Tony Lindgren wrote:
> Hi,
>
> * Tony Lindgren <tony@atomide.com> [160331 10:04]:
>> * Keerthy <a0393675@ti.com> [160331 02:26]:
>>>
>>>
>>> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
>>>> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>>>>>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>>>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>>>>> external
>>>>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>>>>> usually
>>>>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>>>>
>>>>>> Thanks applying into omap-for-v4.6/fixes.
>>>>>
>>>>> Actually let's wait a review from Tero on this one, not sure
>>>>> about the pseudo clock naming here. So dropping for now.
>>>>
>>>> The patch is fine for me, I didn't comment anything before as I thought
>>>> you already applied it.
>>>>
>>>> Acked-by: Tero Kristo <t-kristo@ti.com>
>>>
>>> Thanks Tero.
>>
>> OK applying with Tero's ack.
>
> I'm dropping this again as it introduces new warnings with make dtbs:
>
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra7-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra72-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>
> Regards,
>
> Tony
>

Looks like a merge conflict to me, sys_32k_ck has gone under 
clockdomains for some reason. It should be under clocks.

-Tero

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#1369538

FromTony Lindgren <tony@atomide.com>
Date2016-04-01 21:10 +0200
Message-ID<rjcCd-pj-1@gated-at.bofh.it>
In reply to#1369528
* Tero Kristo <t-kristo@ti.com> [160401 11:50]:
> 
> Looks like a merge conflict to me, sys_32k_ck has gone under clockdomains
> for some reason. It should be under clocks.

Oh OK, I'll wait for an updated patch against v4.6-rc1 then.
Might be worth checking it applies cleanly against
omap-for-v4.6/fixes-rc1 too.

Regards,

Tony

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