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Groups > linux.kernel > #1369349 > unrolled thread
| Started by | Vladimir Murzin <vladimir.murzin@arm.com> |
|---|---|
| First post | 2016-04-01 16:10 +0200 |
| Last post | 2016-04-01 16:10 +0200 |
| Articles | 7 — 2 participants |
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[PATCH v5 00/10] Support for Cortex-M Prototyping System Vladimir Murzin <vladimir.murzin@arm.com> - 2016-04-01 16:10 +0200
[PATCH v5 07/10] ARM: configs: add MPS2 defconfig Vladimir Murzin <vladimir.murzin@arm.com> - 2016-04-01 16:10 +0200
[PATCH v5 04/10] serial: mps2-uart: add MPS2 UART driver Vladimir Murzin <vladimir.murzin@arm.com> - 2016-04-01 16:10 +0200
Re: [PATCH v5 04/10] serial: mps2-uart: add MPS2 UART driver Vladimir Murzin <vladimir.murzin@arm.com> - 2016-04-01 16:30 +0200
Re: [PATCH v5 04/10] serial: mps2-uart: add MPS2 UART driver Andy Shevchenko <andy.shevchenko@gmail.com> - 2016-04-01 16:30 +0200
[PATCH v5 09/10] ARM: dts: introduce MPS2 AN399/AN400 Vladimir Murzin <vladimir.murzin@arm.com> - 2016-04-01 16:10 +0200
[PATCH v5 01/10] dt-bindings: document the MPS2 timer bindings Vladimir Murzin <vladimir.murzin@arm.com> - 2016-04-01 16:10 +0200
| From | Vladimir Murzin <vladimir.murzin@arm.com> |
|---|---|
| Date | 2016-04-01 16:10 +0200 |
| Subject | [PATCH v5 00/10] Support for Cortex-M Prototyping System |
| Message-ID | <rj7VT-5vb-9@gated-at.bofh.it> |
Hi,
This patch series provides the basic support for running ucLinux on V2M-MPS2
platform.
With these patches applied ucLinux can be run on both HW and FVP models
with Cortex-M3/M4/M7 configurations.
Board description:
http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/arm_versatile_express_cortex_m_prototyping_system_(v2m_mps2)_technical_reference_manual_100112_0100_03_en.pdf
Application notes (cover Cortex-M3/M4/M7):
http://infocenter.arm.com/help/topic/com.arm.doc.dai0385a/DAI0385A_cortex_m3_on_v2m_mps2.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.dai0386a/DAI0386A_cortex_m4_on_v2m_mps2.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.dai0399a/DAI0399A_cortex_m7_on_v2m_mps2.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.dai0400a/DAI0400A_cortex_m7_on_v2m_mps2.pdf
Cortex-M System Design Kit (referenced as CMDK from documents above):
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0479c/DDI0479C_cortex_m_system_design_kit_r1p0_trm.pdf
I'd be happy to hear any feedback/comments on this series!
Changelog:
v4 -> v5:
- rebased on 4.6-rc1
- updated mps2-uart per Peter
- s/COFIG_ARCH_MPS2/CONFIG_ARCH_MPS under arm/mach-vexpress
v3 -> v4:
- rebased on 4.5-rc5
- updated mps2-uart per Andy, Alan and Peter
- dropped "zombie" EMBEDDED from defconfg per Arnd
- moved mps2 under vexpress umbrella per Arnd
- updated device-tree sources per Arnd
- dropped low-level debug support, seems earlycon works well for that
v2 -> v3:
- rebased on 4.5-rc4
- fixes for mps2-timer per Thomas
- swicthed back to ttyMPS naming per Greg
v1 -> v2:
- rebased on 4.5-rc2
- fixes for mps2-timer per Daniel and Rob (added Ack from Daniel)
- fixes for mps2-uart per Greg and Andy
RFC -> v1:
- dropped RFC tag
- rebased on 4.4-rc3
- added Acks from Rob
- updated mps2-timer per Daniel
- fixed build failures reported by 0-DAY kernel test infrastructure
Thanks!
Vladimir Murzin (10):
dt-bindings: document the MPS2 timer bindings
clockevents/drivers: add MPS2 Timer driver
dt-bindings: document the MPS2 UART bindings
serial: mps2-uart: add MPS2 UART driver
serial: mps2-uart: add support for early console
ARM: vexpress/mps2: introduce MPS2 platform
ARM: configs: add MPS2 defconfig
ARM: dts: introduce MPS2 AN385/AN386
ARM: dts: introduce MPS2 AN399/AN400
MAINTAINERS: Update ARM Versatile Express platform entry
.../devicetree/bindings/serial/arm,mps2-uart.txt | 19 +
.../devicetree/bindings/timer/arm,mps2-timer.txt | 28 +
MAINTAINERS | 1 +
arch/arm/Kconfig | 8 +
arch/arm/Makefile | 1 +
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/mps2-an385.dts | 92 +++
arch/arm/boot/dts/mps2-an399.dts | 92 +++
arch/arm/boot/dts/mps2.dtsi | 242 ++++++++
arch/arm/configs/mps2_defconfig | 109 ++++
arch/arm/mach-vexpress/Makefile | 4 +-
arch/arm/mach-vexpress/Makefile.boot | 3 +
arch/arm/mach-vexpress/v2m-mps2.c | 21 +
drivers/clocksource/Kconfig | 6 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/mps2-timer.c | 275 +++++++++
drivers/tty/serial/Kconfig | 13 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/mps2-uart.c | 626 ++++++++++++++++++++
include/uapi/linux/serial_core.h | 3 +
20 files changed, 1547 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/serial/arm,mps2-uart.txt
create mode 100644 Documentation/devicetree/bindings/timer/arm,mps2-timer.txt
create mode 100644 arch/arm/boot/dts/mps2-an385.dts
create mode 100644 arch/arm/boot/dts/mps2-an399.dts
create mode 100644 arch/arm/boot/dts/mps2.dtsi
create mode 100644 arch/arm/configs/mps2_defconfig
create mode 100644 arch/arm/mach-vexpress/Makefile.boot
create mode 100644 arch/arm/mach-vexpress/v2m-mps2.c
create mode 100644 drivers/clocksource/mps2-timer.c
create mode 100644 drivers/tty/serial/mps2-uart.c
--
1.7.9.5
[toc] | [next] | [standalone]
| From | Vladimir Murzin <vladimir.murzin@arm.com> |
|---|---|
| Date | 2016-04-01 16:10 +0200 |
| Subject | [PATCH v5 07/10] ARM: configs: add MPS2 defconfig |
| Message-ID | <rj7VW-5vb-35@gated-at.bofh.it> |
| In reply to | #1369349 |
This patch adds a new config for MPS2 platform. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> --- arch/arm/configs/mps2_defconfig | 109 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 arch/arm/configs/mps2_defconfig diff --git a/arch/arm/configs/mps2_defconfig b/arch/arm/configs/mps2_defconfig new file mode 100644 index 0000000..19d119f --- /dev/null +++ b/arch/arm/configs/mps2_defconfig @@ -0,0 +1,109 @@ +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EXPERT=y +# CONFIG_UID16 is not set +# CONFIG_BASE_FULL is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_BLOCK is not set +# CONFIG_MMU is not set +CONFIG_ARCH_MPS2=y +CONFIG_SET_MEM_PARAM=y +CONFIG_DRAM_BASE=0x21000000 +CONFIG_DRAM_SIZE=0x1000000 +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_SHARED_FLAT=y +# CONFIG_COREDUMP is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FW_LOADER is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_CORE is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_MPS2_UART_CONSOLE=y +CONFIG_SERIAL_MPS2_UART=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_MFD_SYSCON=y +# CONFIG_USB_SUPPORT is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_ARM_TIMER_SP804=y +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NLS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_MEMTEST=y -- 1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Vladimir Murzin <vladimir.murzin@arm.com> |
|---|---|
| Date | 2016-04-01 16:10 +0200 |
| Subject | [PATCH v5 04/10] serial: mps2-uart: add MPS2 UART driver |
| Message-ID | <rj7VW-5vb-37@gated-at.bofh.it> |
| In reply to | #1369349 |
This driver adds support to the UART controller found on ARM MPS2
platform.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/tty/serial/Kconfig | 12 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/mps2-uart.c | 598 ++++++++++++++++++++++++++++++++++++++
include/uapi/linux/serial_core.h | 3 +
4 files changed, 614 insertions(+)
create mode 100644 drivers/tty/serial/mps2-uart.c
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 13d4ed6..3673ef0 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1446,6 +1446,18 @@ config SERIAL_EFM32_UART
This driver support the USART and UART ports on
Energy Micro's efm32 SoCs.
+config SERIAL_MPS2_UART_CONSOLE
+ bool "MPS2 UART console support"
+ depends on SERIAL_MPS2_UART
+ select SERIAL_CORE_CONSOLE
+
+config SERIAL_MPS2_UART
+ bool "MPS2 UART port"
+ depends on ARM || COMPILE_TEST
+ select SERIAL_CORE
+ help
+ This driver support the UART ports on ARM MPS2.
+
config SERIAL_EFM32_UART_CONSOLE
bool "EFM32 UART/USART console support"
depends on SERIAL_EFM32_UART=y
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 8c261ad..81e9057 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o
+obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
# GPIOLIB helpers for modem control lines
obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/mps2-uart.c b/drivers/tty/serial/mps2-uart.c
new file mode 100644
index 0000000..1ae0b39
--- /dev/null
+++ b/drivers/tty/serial/mps2-uart.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright (C) 2015 ARM Limited
+ *
+ * Author: Vladimir Murzin <vladimir.murzin@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * TODO: support for SysRq
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/tty_flip.h>
+#include <linux/types.h>
+
+#define SERIAL_NAME "ttyMPS"
+#define DRIVER_NAME "mps2-uart"
+#define MAKE_NAME(x) (DRIVER_NAME # x)
+
+#define UARTn_DATA 0x00
+
+#define UARTn_STATE 0x04
+#define UARTn_STATE_TX_FULL BIT(0)
+#define UARTn_STATE_RX_FULL BIT(1)
+#define UARTn_STATE_TX_OVERRUN BIT(2)
+#define UARTn_STATE_RX_OVERRUN BIT(3)
+
+#define UARTn_CTRL 0x08
+#define UARTn_CTRL_TX_ENABLE BIT(0)
+#define UARTn_CTRL_RX_ENABLE BIT(1)
+#define UARTn_CTRL_TX_INT_ENABLE BIT(2)
+#define UARTn_CTRL_RX_INT_ENABLE BIT(3)
+#define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
+#define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
+
+#define UARTn_INT 0x0c
+#define UARTn_INT_TX BIT(0)
+#define UARTn_INT_RX BIT(1)
+#define UARTn_INT_TX_OVERRUN BIT(2)
+#define UARTn_INT_RX_OVERRUN BIT(3)
+
+#define UARTn_BAUDDIV 0x10
+#define UARTn_BAUDDIV_MASK GENMASK(20, 0)
+
+/*
+ * Helpers to make typical enable/disable operations more readable.
+ */
+#define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
+ UARTn_CTRL_TX_INT_ENABLE |\
+ UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
+
+#define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
+ UARTn_CTRL_RX_INT_ENABLE |\
+ UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
+
+#define MPS2_MAX_PORTS 3
+
+struct mps2_uart_port {
+ struct uart_port port;
+ struct clk *clk;
+ unsigned int tx_irq;
+ unsigned int rx_irq;
+};
+
+static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
+{
+ return container_of(port, struct mps2_uart_port, port);
+}
+
+static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned off)
+{
+ struct mps2_uart_port *mps_port = to_mps2_port(port);
+
+ writeb(val, mps_port->port.membase + off);
+}
+
+static u8 mps2_uart_read8(struct uart_port *port, unsigned off)
+{
+ struct mps2_uart_port *mps_port = to_mps2_port(port);
+
+ return readb(mps_port->port.membase + off);
+}
+
+static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned off)
+{
+ struct mps2_uart_port *mps_port = to_mps2_port(port);
+
+ writel_relaxed(val, mps_port->port.membase + off);
+}
+
+static unsigned int mps2_uart_tx_empty(struct uart_port *port)
+{
+ u8 status = mps2_uart_read8(port, UARTn_STATE);
+
+ return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
+}
+
+static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
+{
+ return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
+}
+
+static void mps2_uart_stop_tx(struct uart_port *port)
+{
+ u8 control = mps2_uart_read8(port, UARTn_CTRL);
+
+ control &= ~UARTn_CTRL_TX_INT_ENABLE;
+
+ mps2_uart_write8(port, control, UARTn_CTRL);
+}
+
+static void mps2_uart_tx_chars(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->state->xmit;
+
+ while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
+ if (port->x_char) {
+ mps2_uart_write8(port, port->x_char, UARTn_DATA);
+ port->x_char = 0;
+ port->icount.tx++;
+ continue;
+ }
+
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port))
+ break;
+
+ mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
+ xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
+ port->icount.tx++;
+ }
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+ if (uart_circ_empty(xmit))
+ mps2_uart_stop_tx(port);
+}
+
+static void mps2_uart_start_tx(struct uart_port *port)
+{
+ u8 control = mps2_uart_read8(port, UARTn_CTRL);
+
+ control |= UARTn_CTRL_TX_INT_ENABLE;
+
+ mps2_uart_write8(port, control, UARTn_CTRL);
+
+ /*
+ * We've just unmasked the TX IRQ and now slow-starting via
+ * polling; if there is enough data to fill up the internal
+ * write buffer in one go, the TX IRQ should assert, at which
+ * point we switch to fully interrupt-driven TX.
+ */
+
+ mps2_uart_tx_chars(port);
+}
+
+static void mps2_uart_stop_rx(struct uart_port *port)
+{
+ u8 control = mps2_uart_read8(port, UARTn_CTRL);
+
+ control &= ~UARTn_CTRL_RX_GRP;
+
+ mps2_uart_write8(port, control, UARTn_CTRL);
+}
+
+static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
+{
+}
+
+static void mps2_uart_rx_chars(struct uart_port *port)
+{
+ struct tty_port *tport = &port->state->port;
+
+ while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
+ u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
+
+ port->icount.rx++;
+ tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
+ }
+
+ tty_flip_buffer_push(tport);
+}
+
+static irqreturn_t mps2_uart_rxirq(int irq, void *data)
+{
+
+ struct uart_port *port = data;
+ u8 irqflag = mps2_uart_read8(port, UARTn_INT);
+
+ if (unlikely(!(irqflag & UARTn_INT_RX)))
+ return IRQ_NONE;
+
+ spin_lock(&port->lock);
+
+ mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
+ mps2_uart_rx_chars(port);
+
+ spin_unlock(&port->lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mps2_uart_txirq(int irq, void *data)
+{
+ struct uart_port *port = data;
+ u8 irqflag = mps2_uart_read8(port, UARTn_INT);
+
+ if (unlikely(!(irqflag & UARTn_INT_TX)))
+ return IRQ_NONE;
+
+ spin_lock(&port->lock);
+
+ mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
+ mps2_uart_tx_chars(port);
+
+ spin_unlock(&port->lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
+{
+ irqreturn_t handled = IRQ_NONE;
+ struct uart_port *port = data;
+ u8 irqflag = mps2_uart_read8(port, UARTn_INT);
+
+ spin_lock(&port->lock);
+
+ if (irqflag & UARTn_INT_RX_OVERRUN) {
+ struct tty_port *tport = &port->state->port;
+
+ mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
+ port->icount.overrun++;
+ tty_insert_flip_char(tport, 0, TTY_OVERRUN);
+ tty_flip_buffer_push(tport);
+ handled = IRQ_HANDLED;
+ }
+
+ /*
+ * It's never been seen in practice and it never *should* happen since
+ * we check if there is enough room in TX buffer before sending data.
+ * So we keep this check in case something suspicious has happened.
+ */
+ if (irqflag & UARTn_INT_TX_OVERRUN) {
+ mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
+ handled = IRQ_HANDLED;
+ }
+
+ spin_unlock(&port->lock);
+
+ return handled;
+}
+
+static int mps2_uart_startup(struct uart_port *port)
+{
+ struct mps2_uart_port *mps_port = to_mps2_port(port);
+ u8 control = mps2_uart_read8(port, UARTn_CTRL);
+ int ret;
+
+ control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
+
+ mps2_uart_write8(port, control, UARTn_CTRL);
+
+ ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
+ MAKE_NAME(-rx), mps_port);
+ if (ret) {
+ dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
+ return ret;
+ }
+
+ ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
+ MAKE_NAME(-tx), mps_port);
+ if (ret) {
+ dev_err(port->dev, "failed to register txirq (%d)\n", ret);
+ goto err_free_rxirq;
+ }
+
+ ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
+ MAKE_NAME(-overrun), mps_port);
+
+ if (ret) {
+ dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
+ goto err_free_txirq;
+ }
+
+ control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
+
+ mps2_uart_write8(port, control, UARTn_CTRL);
+
+ return 0;
+
+err_free_txirq:
+ free_irq(mps_port->tx_irq, mps_port);
+err_free_rxirq:
+ free_irq(mps_port->rx_irq, mps_port);
+
+ return ret;
+}
+
+static void mps2_uart_shutdown(struct uart_port *port)
+{
+ struct mps2_uart_port *mps_port = to_mps2_port(port);
+ u8 control = mps2_uart_read8(port, UARTn_CTRL);
+
+ control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
+
+ mps2_uart_write8(port, control, UARTn_CTRL);
+
+ free_irq(mps_port->rx_irq, mps_port);
+ free_irq(mps_port->tx_irq, mps_port);
+ free_irq(port->irq, mps_port);
+}
+
+static void mps2_uart_set_termios(struct uart_port *port,
+ struct ktermios *termios, struct ktermios *old)
+{
+ unsigned long flags;
+ unsigned int baud, bauddiv;
+
+ termios->c_cflag &= ~(CRTSCTS | CMSPAR);
+ termios->c_cflag &= ~CSIZE;
+ termios->c_cflag |= CS8;
+ termios->c_cflag &= ~PARENB;
+ termios->c_cflag &= ~CSTOPB;
+
+ baud = uart_get_baud_rate(port, termios, old,
+ DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
+ DIV_ROUND_CLOSEST(port->uartclk, 16));
+
+ bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ uart_update_timeout(port, termios->c_cflag, baud);
+ mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ if (tty_termios_baud_rate(termios))
+ tty_termios_encode_baud_rate(termios, baud, baud);
+
+}
+
+static const char *mps2_uart_type(struct uart_port *port)
+{
+ return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
+}
+
+static void mps2_uart_release_port(struct uart_port *port)
+{
+}
+
+static int mps2_uart_request_port(struct uart_port *port)
+{
+ return 0;
+}
+
+static void mps2_uart_config_port(struct uart_port *port, int type)
+{
+ if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
+ port->type = PORT_MPS2UART;
+}
+
+static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
+{
+ return -EINVAL;
+}
+
+static const struct uart_ops mps2_uart_pops = {
+ .tx_empty = mps2_uart_tx_empty,
+ .set_mctrl = mps2_uart_set_mctrl,
+ .get_mctrl = mps2_uart_get_mctrl,
+ .stop_tx = mps2_uart_stop_tx,
+ .start_tx = mps2_uart_start_tx,
+ .stop_rx = mps2_uart_stop_rx,
+ .break_ctl = mps2_uart_break_ctl,
+ .startup = mps2_uart_startup,
+ .shutdown = mps2_uart_shutdown,
+ .set_termios = mps2_uart_set_termios,
+ .type = mps2_uart_type,
+ .release_port = mps2_uart_release_port,
+ .request_port = mps2_uart_request_port,
+ .config_port = mps2_uart_config_port,
+ .verify_port = mps2_uart_verify_port,
+};
+
+static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS];
+
+#ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
+static void mps2_uart_console_putchar(struct uart_port *port, int ch)
+{
+ while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
+ cpu_relax();
+
+ mps2_uart_write8(port, ch, UARTn_DATA);
+}
+
+static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
+{
+ struct uart_port *port = &mps2_uart_ports[co->index].port;
+
+ uart_console_write(port, s, cnt, mps2_uart_console_putchar);
+}
+
+static int mps2_uart_console_setup(struct console *co, char *options)
+{
+ struct mps2_uart_port *mps_port;
+ int baud = 9600;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
+ return -ENODEV;
+
+ mps_port = &mps2_uart_ports[co->index];
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver mps2_uart_driver;
+
+static struct console mps2_uart_console = {
+ .name = SERIAL_NAME,
+ .device = uart_console_device,
+ .write = mps2_uart_console_write,
+ .setup = mps2_uart_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &mps2_uart_driver,
+};
+
+#define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
+
+#else
+#define MPS2_SERIAL_CONSOLE NULL
+#endif
+
+static struct uart_driver mps2_uart_driver = {
+ .driver_name = DRIVER_NAME,
+ .dev_name = SERIAL_NAME,
+ .nr = MPS2_MAX_PORTS,
+ .cons = MPS2_SERIAL_CONSOLE,
+};
+
+static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int id;
+
+ if (!np)
+ return NULL;
+
+ id = of_alias_get_id(np, "serial");
+ if (id < 0)
+ id = 0;
+
+ if (WARN_ON(id >= MPS2_MAX_PORTS))
+ return NULL;
+
+ mps2_uart_ports[id].port.line = id;
+ return &mps2_uart_ports[id];
+}
+
+static int mps2_init_port(struct mps2_uart_port *mps_port,
+ struct platform_device *pdev)
+{
+ struct resource *res;
+ int ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mps_port->port.membase))
+ return PTR_ERR(mps_port->port.membase);
+
+ mps_port->port.mapbase = res->start;
+ mps_port->port.mapsize = resource_size(res);
+
+ mps_port->rx_irq = platform_get_irq(pdev, 0);
+ mps_port->tx_irq = platform_get_irq(pdev, 1);
+ mps_port->port.irq = platform_get_irq(pdev, 2);
+
+ mps_port->port.iotype = UPIO_MEM;
+ mps_port->port.flags = UPF_BOOT_AUTOCONF;
+ mps_port->port.fifosize = 1;
+ mps_port->port.ops = &mps2_uart_pops;
+ mps_port->port.dev = &pdev->dev;
+
+ mps_port->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(mps_port->clk))
+ return PTR_ERR(mps_port->clk);
+
+ ret = clk_prepare_enable(mps_port->clk);
+ if (ret)
+ return ret;
+
+ mps_port->port.uartclk = clk_get_rate(mps_port->clk);
+
+ clk_disable_unprepare(mps_port->clk);
+
+ return ret;
+}
+
+static int mps2_serial_probe(struct platform_device *pdev)
+{
+ struct mps2_uart_port *mps_port;
+ int ret;
+
+ mps_port = mps2_of_get_port(pdev);
+ if (!mps_port)
+ return -ENODEV;
+
+ ret = mps2_init_port(mps_port, pdev);
+ if (ret)
+ return ret;
+
+ ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, mps_port);
+
+ return 0;
+}
+
+static int mps2_serial_remove(struct platform_device *pdev)
+{
+ struct mps2_uart_port *mps_port = platform_get_drvdata(pdev);
+
+ uart_remove_one_port(&mps2_uart_driver, &mps_port->port);
+
+ return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id mps2_match[] = {
+ { .compatible = "arm,mps2-uart", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mps2_match);
+#endif
+
+static struct platform_driver mps2_serial_driver = {
+ .probe = mps2_serial_probe,
+ .remove = mps2_serial_remove,
+
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = of_match_ptr(mps2_match),
+ },
+};
+
+static int __init mps2_uart_init(void)
+{
+ int ret;
+
+ ret = uart_register_driver(&mps2_uart_driver);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_register(&mps2_serial_driver);
+ if (ret)
+ uart_unregister_driver(&mps2_uart_driver);
+
+ return ret;
+}
+module_init(mps2_uart_init);
+
+static void __exit mps2_uart_exit(void)
+{
+ platform_driver_unregister(&mps2_serial_driver);
+ uart_unregister_driver(&mps2_uart_driver);
+}
+module_exit(mps2_uart_exit);
+
+MODULE_AUTHOR("Vladimir Murzin <vladimir.murzin@arm.com>");
+MODULE_DESCRIPTION("MPS2 UART driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index e513a4e..9aef04c 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -264,4 +264,7 @@
/* MVEBU UART */
#define PORT_MVEBU 114
+/* MPS2 UART */
+#define PORT_MPS2UART 115
+
#endif /* _UAPILINUX_SERIAL_CORE_H */
--
1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Vladimir Murzin <vladimir.murzin@arm.com> |
|---|---|
| Date | 2016-04-01 16:30 +0200 |
| Subject | Re: [PATCH v5 04/10] serial: mps2-uart: add MPS2 UART driver |
| Message-ID | <rj8ff-5EH-3@gated-at.bofh.it> |
| In reply to | #1369351 |
On 01/04/16 15:19, Andy Shevchenko wrote: > On Fri, Apr 1, 2016 at 5:02 PM, Vladimir Murzin <vladimir.murzin@arm.com> wrote: >> This driver adds support to the UART controller found on ARM MPS2 >> platform. >> >> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> > > Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> > Thanks, Andy! Vladimir
[toc] | [prev] | [next] | [standalone]
| From | Andy Shevchenko <andy.shevchenko@gmail.com> |
|---|---|
| Date | 2016-04-01 16:30 +0200 |
| Subject | Re: [PATCH v5 04/10] serial: mps2-uart: add MPS2 UART driver |
| Message-ID | <rj8ff-5EH-5@gated-at.bofh.it> |
| In reply to | #1369351 |
On Fri, Apr 1, 2016 at 5:02 PM, Vladimir Murzin <vladimir.murzin@arm.com> wrote:
> This driver adds support to the UART controller found on ARM MPS2
> platform.
>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> ---
> drivers/tty/serial/Kconfig | 12 +
> drivers/tty/serial/Makefile | 1 +
> drivers/tty/serial/mps2-uart.c | 598 ++++++++++++++++++++++++++++++++++++++
> include/uapi/linux/serial_core.h | 3 +
> 4 files changed, 614 insertions(+)
> create mode 100644 drivers/tty/serial/mps2-uart.c
>
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 13d4ed6..3673ef0 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1446,6 +1446,18 @@ config SERIAL_EFM32_UART
> This driver support the USART and UART ports on
> Energy Micro's efm32 SoCs.
>
> +config SERIAL_MPS2_UART_CONSOLE
> + bool "MPS2 UART console support"
> + depends on SERIAL_MPS2_UART
> + select SERIAL_CORE_CONSOLE
> +
> +config SERIAL_MPS2_UART
> + bool "MPS2 UART port"
> + depends on ARM || COMPILE_TEST
> + select SERIAL_CORE
> + help
> + This driver support the UART ports on ARM MPS2.
> +
> config SERIAL_EFM32_UART_CONSOLE
> bool "EFM32 UART/USART console support"
> depends on SERIAL_EFM32_UART=y
> diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
> index 8c261ad..81e9057 100644
> --- a/drivers/tty/serial/Makefile
> +++ b/drivers/tty/serial/Makefile
> @@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
> obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
> obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
> obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o
> +obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
>
> # GPIOLIB helpers for modem control lines
> obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
> diff --git a/drivers/tty/serial/mps2-uart.c b/drivers/tty/serial/mps2-uart.c
> new file mode 100644
> index 0000000..1ae0b39
> --- /dev/null
> +++ b/drivers/tty/serial/mps2-uart.c
> @@ -0,0 +1,598 @@
> +/*
> + * Copyright (C) 2015 ARM Limited
> + *
> + * Author: Vladimir Murzin <vladimir.murzin@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * TODO: support for SysRq
> + */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> +
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/console.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/serial_core.h>
> +#include <linux/tty_flip.h>
> +#include <linux/types.h>
> +
> +#define SERIAL_NAME "ttyMPS"
> +#define DRIVER_NAME "mps2-uart"
> +#define MAKE_NAME(x) (DRIVER_NAME # x)
> +
> +#define UARTn_DATA 0x00
> +
> +#define UARTn_STATE 0x04
> +#define UARTn_STATE_TX_FULL BIT(0)
> +#define UARTn_STATE_RX_FULL BIT(1)
> +#define UARTn_STATE_TX_OVERRUN BIT(2)
> +#define UARTn_STATE_RX_OVERRUN BIT(3)
> +
> +#define UARTn_CTRL 0x08
> +#define UARTn_CTRL_TX_ENABLE BIT(0)
> +#define UARTn_CTRL_RX_ENABLE BIT(1)
> +#define UARTn_CTRL_TX_INT_ENABLE BIT(2)
> +#define UARTn_CTRL_RX_INT_ENABLE BIT(3)
> +#define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
> +#define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
> +
> +#define UARTn_INT 0x0c
> +#define UARTn_INT_TX BIT(0)
> +#define UARTn_INT_RX BIT(1)
> +#define UARTn_INT_TX_OVERRUN BIT(2)
> +#define UARTn_INT_RX_OVERRUN BIT(3)
> +
> +#define UARTn_BAUDDIV 0x10
> +#define UARTn_BAUDDIV_MASK GENMASK(20, 0)
> +
> +/*
> + * Helpers to make typical enable/disable operations more readable.
> + */
> +#define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
> + UARTn_CTRL_TX_INT_ENABLE |\
> + UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
> +
> +#define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
> + UARTn_CTRL_RX_INT_ENABLE |\
> + UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
> +
> +#define MPS2_MAX_PORTS 3
> +
> +struct mps2_uart_port {
> + struct uart_port port;
> + struct clk *clk;
> + unsigned int tx_irq;
> + unsigned int rx_irq;
> +};
> +
> +static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
> +{
> + return container_of(port, struct mps2_uart_port, port);
> +}
> +
> +static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned off)
> +{
> + struct mps2_uart_port *mps_port = to_mps2_port(port);
> +
> + writeb(val, mps_port->port.membase + off);
> +}
> +
> +static u8 mps2_uart_read8(struct uart_port *port, unsigned off)
> +{
> + struct mps2_uart_port *mps_port = to_mps2_port(port);
> +
> + return readb(mps_port->port.membase + off);
> +}
> +
> +static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned off)
> +{
> + struct mps2_uart_port *mps_port = to_mps2_port(port);
> +
> + writel_relaxed(val, mps_port->port.membase + off);
> +}
> +
> +static unsigned int mps2_uart_tx_empty(struct uart_port *port)
> +{
> + u8 status = mps2_uart_read8(port, UARTn_STATE);
> +
> + return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
> +}
> +
> +static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
> +{
> +}
> +
> +static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
> +{
> + return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
> +}
> +
> +static void mps2_uart_stop_tx(struct uart_port *port)
> +{
> + u8 control = mps2_uart_read8(port, UARTn_CTRL);
> +
> + control &= ~UARTn_CTRL_TX_INT_ENABLE;
> +
> + mps2_uart_write8(port, control, UARTn_CTRL);
> +}
> +
> +static void mps2_uart_tx_chars(struct uart_port *port)
> +{
> + struct circ_buf *xmit = &port->state->xmit;
> +
> + while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
> + if (port->x_char) {
> + mps2_uart_write8(port, port->x_char, UARTn_DATA);
> + port->x_char = 0;
> + port->icount.tx++;
> + continue;
> + }
> +
> + if (uart_circ_empty(xmit) || uart_tx_stopped(port))
> + break;
> +
> + mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
> + xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
> + port->icount.tx++;
> + }
> +
> + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
> + uart_write_wakeup(port);
> +
> + if (uart_circ_empty(xmit))
> + mps2_uart_stop_tx(port);
> +}
> +
> +static void mps2_uart_start_tx(struct uart_port *port)
> +{
> + u8 control = mps2_uart_read8(port, UARTn_CTRL);
> +
> + control |= UARTn_CTRL_TX_INT_ENABLE;
> +
> + mps2_uart_write8(port, control, UARTn_CTRL);
> +
> + /*
> + * We've just unmasked the TX IRQ and now slow-starting via
> + * polling; if there is enough data to fill up the internal
> + * write buffer in one go, the TX IRQ should assert, at which
> + * point we switch to fully interrupt-driven TX.
> + */
> +
> + mps2_uart_tx_chars(port);
> +}
> +
> +static void mps2_uart_stop_rx(struct uart_port *port)
> +{
> + u8 control = mps2_uart_read8(port, UARTn_CTRL);
> +
> + control &= ~UARTn_CTRL_RX_GRP;
> +
> + mps2_uart_write8(port, control, UARTn_CTRL);
> +}
> +
> +static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
> +{
> +}
> +
> +static void mps2_uart_rx_chars(struct uart_port *port)
> +{
> + struct tty_port *tport = &port->state->port;
> +
> + while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
> + u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
> +
> + port->icount.rx++;
> + tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
> + }
> +
> + tty_flip_buffer_push(tport);
> +}
> +
> +static irqreturn_t mps2_uart_rxirq(int irq, void *data)
> +{
> +
> + struct uart_port *port = data;
> + u8 irqflag = mps2_uart_read8(port, UARTn_INT);
> +
> + if (unlikely(!(irqflag & UARTn_INT_RX)))
> + return IRQ_NONE;
> +
> + spin_lock(&port->lock);
> +
> + mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
> + mps2_uart_rx_chars(port);
> +
> + spin_unlock(&port->lock);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t mps2_uart_txirq(int irq, void *data)
> +{
> + struct uart_port *port = data;
> + u8 irqflag = mps2_uart_read8(port, UARTn_INT);
> +
> + if (unlikely(!(irqflag & UARTn_INT_TX)))
> + return IRQ_NONE;
> +
> + spin_lock(&port->lock);
> +
> + mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
> + mps2_uart_tx_chars(port);
> +
> + spin_unlock(&port->lock);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
> +{
> + irqreturn_t handled = IRQ_NONE;
> + struct uart_port *port = data;
> + u8 irqflag = mps2_uart_read8(port, UARTn_INT);
> +
> + spin_lock(&port->lock);
> +
> + if (irqflag & UARTn_INT_RX_OVERRUN) {
> + struct tty_port *tport = &port->state->port;
> +
> + mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
> + port->icount.overrun++;
> + tty_insert_flip_char(tport, 0, TTY_OVERRUN);
> + tty_flip_buffer_push(tport);
> + handled = IRQ_HANDLED;
> + }
> +
> + /*
> + * It's never been seen in practice and it never *should* happen since
> + * we check if there is enough room in TX buffer before sending data.
> + * So we keep this check in case something suspicious has happened.
> + */
> + if (irqflag & UARTn_INT_TX_OVERRUN) {
> + mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
> + handled = IRQ_HANDLED;
> + }
> +
> + spin_unlock(&port->lock);
> +
> + return handled;
> +}
> +
> +static int mps2_uart_startup(struct uart_port *port)
> +{
> + struct mps2_uart_port *mps_port = to_mps2_port(port);
> + u8 control = mps2_uart_read8(port, UARTn_CTRL);
> + int ret;
> +
> + control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
> +
> + mps2_uart_write8(port, control, UARTn_CTRL);
> +
> + ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
> + MAKE_NAME(-rx), mps_port);
> + if (ret) {
> + dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
> + return ret;
> + }
> +
> + ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
> + MAKE_NAME(-tx), mps_port);
> + if (ret) {
> + dev_err(port->dev, "failed to register txirq (%d)\n", ret);
> + goto err_free_rxirq;
> + }
> +
> + ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
> + MAKE_NAME(-overrun), mps_port);
> +
> + if (ret) {
> + dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
> + goto err_free_txirq;
> + }
> +
> + control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
> +
> + mps2_uart_write8(port, control, UARTn_CTRL);
> +
> + return 0;
> +
> +err_free_txirq:
> + free_irq(mps_port->tx_irq, mps_port);
> +err_free_rxirq:
> + free_irq(mps_port->rx_irq, mps_port);
> +
> + return ret;
> +}
> +
> +static void mps2_uart_shutdown(struct uart_port *port)
> +{
> + struct mps2_uart_port *mps_port = to_mps2_port(port);
> + u8 control = mps2_uart_read8(port, UARTn_CTRL);
> +
> + control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
> +
> + mps2_uart_write8(port, control, UARTn_CTRL);
> +
> + free_irq(mps_port->rx_irq, mps_port);
> + free_irq(mps_port->tx_irq, mps_port);
> + free_irq(port->irq, mps_port);
> +}
> +
> +static void mps2_uart_set_termios(struct uart_port *port,
> + struct ktermios *termios, struct ktermios *old)
> +{
> + unsigned long flags;
> + unsigned int baud, bauddiv;
> +
> + termios->c_cflag &= ~(CRTSCTS | CMSPAR);
> + termios->c_cflag &= ~CSIZE;
> + termios->c_cflag |= CS8;
> + termios->c_cflag &= ~PARENB;
> + termios->c_cflag &= ~CSTOPB;
> +
> + baud = uart_get_baud_rate(port, termios, old,
> + DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
> + DIV_ROUND_CLOSEST(port->uartclk, 16));
> +
> + bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
> +
> + spin_lock_irqsave(&port->lock, flags);
> +
> + uart_update_timeout(port, termios->c_cflag, baud);
> + mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
> +
> + spin_unlock_irqrestore(&port->lock, flags);
> +
> + if (tty_termios_baud_rate(termios))
> + tty_termios_encode_baud_rate(termios, baud, baud);
> +
> +}
> +
> +static const char *mps2_uart_type(struct uart_port *port)
> +{
> + return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
> +}
> +
> +static void mps2_uart_release_port(struct uart_port *port)
> +{
> +}
> +
> +static int mps2_uart_request_port(struct uart_port *port)
> +{
> + return 0;
> +}
> +
> +static void mps2_uart_config_port(struct uart_port *port, int type)
> +{
> + if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
> + port->type = PORT_MPS2UART;
> +}
> +
> +static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
> +{
> + return -EINVAL;
> +}
> +
> +static const struct uart_ops mps2_uart_pops = {
> + .tx_empty = mps2_uart_tx_empty,
> + .set_mctrl = mps2_uart_set_mctrl,
> + .get_mctrl = mps2_uart_get_mctrl,
> + .stop_tx = mps2_uart_stop_tx,
> + .start_tx = mps2_uart_start_tx,
> + .stop_rx = mps2_uart_stop_rx,
> + .break_ctl = mps2_uart_break_ctl,
> + .startup = mps2_uart_startup,
> + .shutdown = mps2_uart_shutdown,
> + .set_termios = mps2_uart_set_termios,
> + .type = mps2_uart_type,
> + .release_port = mps2_uart_release_port,
> + .request_port = mps2_uart_request_port,
> + .config_port = mps2_uart_config_port,
> + .verify_port = mps2_uart_verify_port,
> +};
> +
> +static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS];
> +
> +#ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
> +static void mps2_uart_console_putchar(struct uart_port *port, int ch)
> +{
> + while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
> + cpu_relax();
> +
> + mps2_uart_write8(port, ch, UARTn_DATA);
> +}
> +
> +static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
> +{
> + struct uart_port *port = &mps2_uart_ports[co->index].port;
> +
> + uart_console_write(port, s, cnt, mps2_uart_console_putchar);
> +}
> +
> +static int mps2_uart_console_setup(struct console *co, char *options)
> +{
> + struct mps2_uart_port *mps_port;
> + int baud = 9600;
> + int bits = 8;
> + int parity = 'n';
> + int flow = 'n';
> +
> + if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
> + return -ENODEV;
> +
> + mps_port = &mps2_uart_ports[co->index];
> +
> + if (options)
> + uart_parse_options(options, &baud, &parity, &bits, &flow);
> +
> + return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
> +}
> +
> +static struct uart_driver mps2_uart_driver;
> +
> +static struct console mps2_uart_console = {
> + .name = SERIAL_NAME,
> + .device = uart_console_device,
> + .write = mps2_uart_console_write,
> + .setup = mps2_uart_console_setup,
> + .flags = CON_PRINTBUFFER,
> + .index = -1,
> + .data = &mps2_uart_driver,
> +};
> +
> +#define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
> +
> +#else
> +#define MPS2_SERIAL_CONSOLE NULL
> +#endif
> +
> +static struct uart_driver mps2_uart_driver = {
> + .driver_name = DRIVER_NAME,
> + .dev_name = SERIAL_NAME,
> + .nr = MPS2_MAX_PORTS,
> + .cons = MPS2_SERIAL_CONSOLE,
> +};
> +
> +static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + int id;
> +
> + if (!np)
> + return NULL;
> +
> + id = of_alias_get_id(np, "serial");
> + if (id < 0)
> + id = 0;
> +
> + if (WARN_ON(id >= MPS2_MAX_PORTS))
> + return NULL;
> +
> + mps2_uart_ports[id].port.line = id;
> + return &mps2_uart_ports[id];
> +}
> +
> +static int mps2_init_port(struct mps2_uart_port *mps_port,
> + struct platform_device *pdev)
> +{
> + struct resource *res;
> + int ret;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(mps_port->port.membase))
> + return PTR_ERR(mps_port->port.membase);
> +
> + mps_port->port.mapbase = res->start;
> + mps_port->port.mapsize = resource_size(res);
> +
> + mps_port->rx_irq = platform_get_irq(pdev, 0);
> + mps_port->tx_irq = platform_get_irq(pdev, 1);
> + mps_port->port.irq = platform_get_irq(pdev, 2);
> +
> + mps_port->port.iotype = UPIO_MEM;
> + mps_port->port.flags = UPF_BOOT_AUTOCONF;
> + mps_port->port.fifosize = 1;
> + mps_port->port.ops = &mps2_uart_pops;
> + mps_port->port.dev = &pdev->dev;
> +
> + mps_port->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(mps_port->clk))
> + return PTR_ERR(mps_port->clk);
> +
> + ret = clk_prepare_enable(mps_port->clk);
> + if (ret)
> + return ret;
> +
> + mps_port->port.uartclk = clk_get_rate(mps_port->clk);
> +
> + clk_disable_unprepare(mps_port->clk);
> +
> + return ret;
> +}
> +
> +static int mps2_serial_probe(struct platform_device *pdev)
> +{
> + struct mps2_uart_port *mps_port;
> + int ret;
> +
> + mps_port = mps2_of_get_port(pdev);
> + if (!mps_port)
> + return -ENODEV;
> +
> + ret = mps2_init_port(mps_port, pdev);
> + if (ret)
> + return ret;
> +
> + ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, mps_port);
> +
> + return 0;
> +}
> +
> +static int mps2_serial_remove(struct platform_device *pdev)
> +{
> + struct mps2_uart_port *mps_port = platform_get_drvdata(pdev);
> +
> + uart_remove_one_port(&mps2_uart_driver, &mps_port->port);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id mps2_match[] = {
> + { .compatible = "arm,mps2-uart", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mps2_match);
> +#endif
> +
> +static struct platform_driver mps2_serial_driver = {
> + .probe = mps2_serial_probe,
> + .remove = mps2_serial_remove,
> +
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = of_match_ptr(mps2_match),
> + },
> +};
> +
> +static int __init mps2_uart_init(void)
> +{
> + int ret;
> +
> + ret = uart_register_driver(&mps2_uart_driver);
> + if (ret)
> + return ret;
> +
> + ret = platform_driver_register(&mps2_serial_driver);
> + if (ret)
> + uart_unregister_driver(&mps2_uart_driver);
> +
> + return ret;
> +}
> +module_init(mps2_uart_init);
> +
> +static void __exit mps2_uart_exit(void)
> +{
> + platform_driver_unregister(&mps2_serial_driver);
> + uart_unregister_driver(&mps2_uart_driver);
> +}
> +module_exit(mps2_uart_exit);
> +
> +MODULE_AUTHOR("Vladimir Murzin <vladimir.murzin@arm.com>");
> +MODULE_DESCRIPTION("MPS2 UART driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:" DRIVER_NAME);
> diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
> index e513a4e..9aef04c 100644
> --- a/include/uapi/linux/serial_core.h
> +++ b/include/uapi/linux/serial_core.h
> @@ -264,4 +264,7 @@
> /* MVEBU UART */
> #define PORT_MVEBU 114
>
> +/* MPS2 UART */
> +#define PORT_MPS2UART 115
> +
> #endif /* _UAPILINUX_SERIAL_CORE_H */
> --
> 1.7.9.5
>
--
With Best Regards,
Andy Shevchenko
[toc] | [prev] | [next] | [standalone]
| From | Vladimir Murzin <vladimir.murzin@arm.com> |
|---|---|
| Date | 2016-04-01 16:10 +0200 |
| Subject | [PATCH v5 09/10] ARM: dts: introduce MPS2 AN399/AN400 |
| Message-ID | <rj7VW-5vb-41@gated-at.bofh.it> |
| In reply to | #1369349 |
Application Notes 399 and 400 shares the same memory map and
features. Both are shipped with Cortex-M7 and have the same peripheral
as AN385/AN386, but with different location of PSRAM and Ethernet
controller.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/mps2-an399.dts | 92 ++++++++++++++++++++++++++++++++++++++
2 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/mps2-an399.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1efa5a2..c7a78c9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -253,7 +253,9 @@ dtb-$(CONFIG_ARCH_MMP) += \
dtb-$(CONFIG_MACH_MESON8B) += \
meson8b-mxq.dtb \
meson8b-odroidc1.dtb
-dtb-$(CONFIG_ARCH_MPS2) += mps2-an385.dtb
+dtb-$(CONFIG_ARCH_MPS2) += \
+ mps2-an385.dtb \
+ mps2-an399.dtb
dtb-$(CONFIG_ARCH_MOXART) += \
moxart-uc7112lx.dtb
dtb-$(CONFIG_SOC_IMX1) += \
diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/mps2-an399.dts
new file mode 100644
index 0000000..776595f
--- /dev/null
+++ b/arch/arm/boot/dts/mps2-an399.dts
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2015 ARM Limited
+ *
+ * Author: Vladimir Murzin <vladimir.murzin@arm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "mps2.dtsi"
+
+/ {
+ model = "ARM MPS2 Application Note 399/400";
+ compatible = "arm,mps2";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "rdinit=/sbin/init earlycon";
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x1000000>;
+ };
+
+ smb {
+ ethernet@1,0 {
+ compatible = "smsc,lan9220", "smsc,lan9115";
+ reg = <1 0x0 0x10000>;
+ interrupts = <13>;
+ interrupt-parent = <&nvic>;
+ smsc,irq-active-high;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&timer1 {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
--
1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Vladimir Murzin <vladimir.murzin@arm.com> |
|---|---|
| Date | 2016-04-01 16:10 +0200 |
| Subject | [PATCH v5 01/10] dt-bindings: document the MPS2 timer bindings |
| Message-ID | <rj7VW-5vb-43@gated-at.bofh.it> |
| In reply to | #1369349 |
This adds documentation of device tree bindings for the
timers found on ARM MPS2 platform.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/timer/arm,mps2-timer.txt | 28 ++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/arm,mps2-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt b/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt
new file mode 100644
index 0000000..48f84d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt
@@ -0,0 +1,28 @@
+ARM MPS2 timer
+
+The MPS2 platform has simple general-purpose 32 bits timers.
+
+Required properties:
+- compatible : Should be "arm,mps2-timer"
+- reg : Address and length of the register set
+- interrupts : Reference to the timer interrupt
+
+Required clocking property, have to be one of:
+- clocks : The input clock of the timer
+- clock-frequency : The rate in HZ in input of the ARM MPS2 timer
+
+Examples:
+
+timer1: mps2-timer@40000000 {
+ compatible = "arm,mps2-timer";
+ reg = <0x40000000 0x1000>;
+ interrupts = <8>;
+ clocks = <&sysclk>;
+};
+
+timer2: mps2-timer@40001000 {
+ compatible = "arm,mps2-timer";
+ reg = <0x40001000 0x1000>;
+ interrupts = <9>;
+ clock-frequency = <25000000>;
+};
--
1.7.9.5
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