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[PATCH v2 0/6] Add pinctrl support for Baytrail

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  [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan <cristina.ciocan@intel.com> - 2016-03-28 15:30 +0200
    Re: [PATCH v2 0/6] Add pinctrl support for Baytrail Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-03-30 16:50 +0200

#1365494 — [PATCH v2 0/6] Add pinctrl support for Baytrail

Add support for pin control (pin muxing and pin configuration) for Baytrail
platform.

It follows the design in pinctrl-intel.c, but could not use the
implementation in pinctrl-intel since there were significant differences:
	- gpio pin pads are not ordered
	- per group functions: for setting a certain mode, there are groups
	that need setting pins with different values; for instance, for
	setting USB ULPI pins to GPIO function, pin 2 (GPIO_SUS1) needs
	to be set to function 1, wihle all other from the group need to be
	set to 0
	- communities only need pin base and count as specific data
	- irq set type only clears all flags, while the actual type setting
	is made in the byt_irq_unmask function, which does not comply with
	the intel pinctrl implementation

Changes from v1:
	- fix reg, reg_val and byt_soc_data not used variables warnings

Cristina Ciocan (6):
  pinctrl: baytrail: Add pin control data structures
  pinctrl: baytrail: Add pin control operations
  pinctrl: baytrail: Update gpio chip operations
  pinctrl: baytrail: Update irq chip operations
  pinctrl: baytrail: Register pin control handling
  pinctrl: baytrail: Add debounce configuration

 drivers/pinctrl/intel/Kconfig            |    3 +
 drivers/pinctrl/intel/pinctrl-baytrail.c | 1690 +++++++++++++++++++++++++-----
 2 files changed, 1444 insertions(+), 249 deletions(-)

--
1.9.1

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#1367257

On Mon, Mar 28, 2016 at 04:29:34PM +0300, Cristina Ciocan wrote:
> Add support for pin control (pin muxing and pin configuration) for Baytrail
> platform.
> 
> It follows the design in pinctrl-intel.c, but could not use the
> implementation in pinctrl-intel since there were significant differences:
> 	- gpio pin pads are not ordered
> 	- per group functions: for setting a certain mode, there are groups
> 	that need setting pins with different values; for instance, for
> 	setting USB ULPI pins to GPIO function, pin 2 (GPIO_SUS1) needs
> 	to be set to function 1, wihle all other from the group need to be
> 	set to 0
> 	- communities only need pin base and count as specific data
> 	- irq set type only clears all flags, while the actual type setting
> 	is made in the byt_irq_unmask function, which does not comply with
> 	the intel pinctrl implementation
> 
> Changes from v1:
> 	- fix reg, reg_val and byt_soc_data not used variables warnings
> 
> Cristina Ciocan (6):
>   pinctrl: baytrail: Add pin control data structures
>   pinctrl: baytrail: Add pin control operations
>   pinctrl: baytrail: Update gpio chip operations
>   pinctrl: baytrail: Update irq chip operations
>   pinctrl: baytrail: Register pin control handling
>   pinctrl: baytrail: Add debounce configuration

Apart of the pin naming I commented, this patch series finally
brings real pinctrl support to the misnamed baytrail GPIO driver which
is definitely the right thing to do :)

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

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