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Groups > linux.kernel > #1366204 > unrolled thread
| Started by | "Winkler, Tomas" <tomas.winkler@intel.com> |
|---|---|
| First post | 2016-03-29 14:20 +0200 |
| Last post | 2016-03-30 12:00 +0200 |
| Articles | 2 — 2 participants |
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RE: [RESEND] [PATCH v11 3/6] added support for DesignWare Controller "Winkler, Tomas" <tomas.winkler@intel.com> - 2016-03-29 14:20 +0200
Re: [RESEND] [PATCH v11 3/6] added support for DesignWare Controller Joao Pinto <Joao.Pinto@synopsys.com> - 2016-03-30 12:00 +0200
| From | "Winkler, Tomas" <tomas.winkler@intel.com> |
|---|---|
| Date | 2016-03-29 14:20 +0200 |
| Subject | RE: [RESEND] [PATCH v11 3/6] added support for DesignWare Controller |
| Message-ID | <ri0MO-65P-1@gated-at.bofh.it> |
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index 2570d94..8b0cdf0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -262,6 +262,7 @@ struct ufs_pwr_mode_info {
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
+ * @custom_phy_initialization: used to initialize phys in DWC Cores
*/
struct ufs_hba_variant_ops {
const char *name;
@@ -283,6 +284,7 @@ struct ufs_hba_variant_ops {
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
void (*dbg_register_dump)(struct ufs_hba *hba);
+ int (*custom_phy_initialization)(struct ufs_hba *);
};
I think just drop custom_ prefix these handlers are for customization so this doesn't add any information
Also here, I prefer that infrastructure changes will be in separate patches and not mangled with a specific device patch.
/* clock gating state */
diff --git a/drivers/scsi/ufs/ufshci-dwc.h b/drivers/scsi/ufs/ufshci-dwc.h new file mode 100644 index 0000000..947a75c
--- /dev/null
+++ b/drivers/scsi/ufs/ufshci-dwc.h
@@ -0,0 +1,42 @@
+/*
+ * UFS Host driver for Synopsys Designware Core
+ *
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Authors: Joao Pinto <jpinto@synopsys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _UFSHCI_DWC_H
+#define _UFSHCI_DWC_H
+
+/* DWC HC UFSHCI specific Registers */
+enum dwc_specific_registers {
+ DWC_UFS_REG_HCLKDIV = 0xFC,
+};
+
+/* Link Status*/
+enum link_status {
+ UFSHCD_LINK_IS_DOWN = 1,
+ UFSHCD_LINK_IS_UP = 2,
+};
Is is designware specific ? Then should probably be DWC_ prefixed, if not then shouldn't be defined here.
+#endif /* End of Header */
diff --git a/drivers/scsi/ufs/unipro.h b/drivers/scsi/ufs/unipro.h index 816a8a4..da16254 100644
--- a/drivers/scsi/ufs/unipro.h
+++ b/drivers/scsi/ufs/unipro.h
Should also go to a separate patch ?
@@ -35,6 +35,10 @@
#define TX_LCC_SEQUENCER 0x0032
#define TX_MIN_ACTIVATETIME 0x0033
#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
+#define TX_REFCLKFREQ 0x00EB
+#define TX_CFGCLKFREQVAL 0x00EC
+#define CFGEXTRATTR 0x00F0
+#define DITHERCTRL2 0x00F1
/*
* M-RX Configuration Attributes
@@ -48,8 +52,38 @@
#define RX_ENTER_HIBERN8 0x00A7
#define RX_BYPASS_8B10B_ENABLE 0x00A8
#define RX_TERMINATION_FORCE_ENABLE 0x0089
+#define RX_REFCLKFREQ 0x00EB
+#define RX_CFGCLKFREQVAL 0x00EC
+#define CFGWIDEINLN 0x00F0
+#define CFGRXCDR8 0x00BA
+#define ENARXDIRECTCFG4 0x00F2
+#define CFGRXOVR8 0x00BD
+#define RXDIRECTCTRL2 0x00C7
+#define ENARXDIRECTCFG3 0x00F3
+#define RXCALCTRL 0x00B4
+#define ENARXDIRECTCFG2 0x00F4
+#define CFGRXOVR4 0x00E9
+#define RXSQCTRL 0x00B5
+#define CFGRXOVR6 0x00BF
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
+
+/*
+ * Common Block Attributes
+ */
+#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
+#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
+#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
+#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
+#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
+#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
+#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
+#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
+#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
+#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
+
+#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
+
/*
* PHY Adpater attributes
*/
@@ -110,6 +144,11 @@
#define PA_STALLNOCONFIGTIME 0x15A3
#define PA_SAVECONFIGTIME 0x15A4
+/*Other attributes*/
+#define VS_MPHYCFGUPDT 0xD085
+#define VS_DEBUGOMC 0xD09E
+#define VS_POWERSTATE 0xD083
+
/* PA power modes */
enum {
FAST_MODE = 1,
--
1.8.1.5
--
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| From | Joao Pinto <Joao.Pinto@synopsys.com> |
|---|---|
| Date | 2016-03-30 12:00 +0200 |
| Message-ID | <ril4T-3q2-17@gated-at.bofh.it> |
| In reply to | #1366204 |
Hi Thomas,
On 3/29/2016 1:15 PM, Winkler, Tomas wrote:
>
> diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index 2570d94..8b0cdf0 100644
> --- a/drivers/scsi/ufs/ufshcd.h
> +++ b/drivers/scsi/ufs/ufshcd.h
> @@ -262,6 +262,7 @@ struct ufs_pwr_mode_info {
> * @suspend: called during host controller PM callback
> * @resume: called during host controller PM callback
> * @dbg_register_dump: used to dump controller debug information
> + * @custom_phy_initialization: used to initialize phys in DWC Cores
> */
> struct ufs_hba_variant_ops {
> const char *name;
> @@ -283,6 +284,7 @@ struct ufs_hba_variant_ops {
> int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
> int (*resume)(struct ufs_hba *, enum ufs_pm_op);
> void (*dbg_register_dump)(struct ufs_hba *hba);
[snip]...
> /*
> * PHY Adpater attributes
> */
> @@ -110,6 +144,11 @@
> #define PA_STALLNOCONFIGTIME 0x15A3
> #define PA_SAVECONFIGTIME 0x15A4
>
> +/*Other attributes*/
> +#define VS_MPHYCFGUPDT 0xD085
> +#define VS_DEBUGOMC 0xD09E
> +#define VS_POWERSTATE 0xD083
> +
> /* PA power modes */
> enum {
> FAST_MODE = 1,
> --
> 1.8.1.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
>
I am planning to start working today in the v12 of the patch-set. Did you have
opportunity to check the other patches (4, 5 and 6)?
Thanks,
Joao
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