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[PATCH 0/3] move Rockchip usbphy under the GRF mfd

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  [PATCH 0/3] move Rockchip usbphy under the GRF mfd Heiko Stuebner <heiko@sntech.de> - 2016-03-31 15:50 +0200
    [PATCH 2/3] ARM: dts: rockchip: make rk3288-grf a simple-mfd Heiko Stuebner <heiko@sntech.de> - 2016-03-31 15:50 +0200
    [PATCH 3/3] ARM: dts: rockchip: move rk3288 usbphy under the GRF node Heiko Stuebner <heiko@sntech.de> - 2016-03-31 15:50 +0200

#1368311 — [PATCH 0/3] move Rockchip usbphy under the GRF mfd

The usb2 phy used on rk3288 and before is fully part of the
GRF, so similar to other phys repositioned recently, it
should live under GRF node as well.

Patch 1 should go through the phy-tree, hopefully into 4.7
and I'll pick patches 2 and 3 myself for 4.8 then.


Heiko Stuebner (3):
  phy: rockchip-usb: should be a child device of the GRF
  ARM: dts: rockchip: make rk3288-grf a simple-mfd
  ARM: dts: rockchip: move rk3288 usbphy under the GRF node

 .../devicetree/bindings/phy/rockchip-usb-phy.txt   | 27 +++++----
 arch/arm/boot/dts/rk3288.dtsi                      | 65 +++++++++++-----------
 drivers/phy/phy-rockchip-usb.c                     | 14 ++++-
 3 files changed, 60 insertions(+), 46 deletions(-)

-- 
2.6.4

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#1368315 — [PATCH 2/3] ARM: dts: rockchip: make rk3288-grf a simple-mfd

Similar to the pmu, the general register files contain a lot of different
setting bits grouped into general registers, but also some somewhat special
entities like the controls for some phy-blocks or the io-voltage control.
To be able to move these blocks under the grf node where they actually
belong, make it a simple-mfd.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3288.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 31f7e20..bc57232 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -745,7 +745,7 @@
 	};
 
 	grf: syscon@ff770000 {
-		compatible = "rockchip,rk3288-grf", "syscon";
+		compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 		reg = <0xff770000 0x1000>;
 	};
 
-- 
2.6.4

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#1368317 — [PATCH 3/3] ARM: dts: rockchip: move rk3288 usbphy under the GRF node

The rk3288 usbphy is completely enclosed in the general register files
and the updated binding allows it to be a subnode of the GRF now.
So move the node appropriately.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3288.dtsi | 63 +++++++++++++++++++++----------------------
 1 file changed, 31 insertions(+), 32 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index bc57232..e746d35 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -747,6 +747,37 @@
 	grf: syscon@ff770000 {
 		compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 		reg = <0xff770000 0x1000>;
+
+		usbphy: usbphy {
+			compatible = "rockchip,rk3288-usb-phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			usbphy0: usb-phy0 {
+				#phy-cells = <0>;
+				reg = <0x320>;
+				clocks = <&cru SCLK_OTGPHY0>;
+				clock-names = "phyclk";
+				#clock-cells = <0>;
+			};
+
+			usbphy1: usb-phy1 {
+				#phy-cells = <0>;
+				reg = <0x334>;
+				clocks = <&cru SCLK_OTGPHY1>;
+				clock-names = "phyclk";
+				#clock-cells = <0>;
+			};
+
+			usbphy2: usb-phy2 {
+				#phy-cells = <0>;
+				reg = <0x348>;
+				clocks = <&cru SCLK_OTGPHY2>;
+				clock-names = "phyclk";
+				#clock-cells = <0>;
+			};
+		};
 	};
 
 	wdt: watchdog@ff800000 {
@@ -959,38 +990,6 @@
 		};
 	};
 
-	usbphy: phy {
-		compatible = "rockchip,rk3288-usb-phy";
-		rockchip,grf = <&grf>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-
-		usbphy0: usb-phy0 {
-			#phy-cells = <0>;
-			reg = <0x320>;
-			clocks = <&cru SCLK_OTGPHY0>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-		};
-
-		usbphy1: usb-phy1 {
-			#phy-cells = <0>;
-			reg = <0x334>;
-			clocks = <&cru SCLK_OTGPHY1>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-		};
-
-		usbphy2: usb-phy2 {
-			#phy-cells = <0>;
-			reg = <0x348>;
-			clocks = <&cru SCLK_OTGPHY2>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-		};
-	};
-
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3288-pinctrl";
 		rockchip,grf = <&grf>;
-- 
2.6.4

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