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| Started by | Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> |
|---|---|
| First post | 2016-03-26 19:50 +0100 |
| Last post | 2016-03-29 11:20 +0200 |
| Articles | 3 — 3 participants |
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[PATCH] x86: cpufreq: remove duplicated TDP MSR macro definitions Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> - 2016-03-26 19:50 +0100
Re: [PATCH] x86: cpufreq: remove duplicated TDP MSR macro definitions Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> - 2016-03-28 22:10 +0200
[tip:x86/urgent] x86/cpufreq: Remove duplicated TDP MSR macro definitions tip-bot for Vladimir Zapolskiy <tipbot@zytor.com> - 2016-03-29 11:20 +0200
| From | Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> |
|---|---|
| Date | 2016-03-26 19:50 +0100 |
| Subject | [PATCH] x86: cpufreq: remove duplicated TDP MSR macro definitions |
| Message-ID | <rh1rA-4Jn-13@gated-at.bofh.it> |
The list of CPU model specific registers contains two copies of TDP
registers, remove the one, which is out of numerical order in the
list.
Fixes: 6a35fc2d6c22 ("cpufreq: intel_pstate: get P1 from TAR when available")
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
---
arch/x86/include/asm/msr-index.h | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 2da46ac..426e946 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -190,6 +190,7 @@
#define MSR_PP1_ENERGY_STATUS 0x00000641
#define MSR_PP1_POLICY 0x00000642
+/* Config TDP MSRs */
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
@@ -210,13 +211,6 @@
#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
-/* Config TDP MSRs */
-#define MSR_CONFIG_TDP_NOMINAL 0x00000648
-#define MSR_CONFIG_TDP_LEVEL1 0x00000649
-#define MSR_CONFIG_TDP_LEVEL2 0x0000064A
-#define MSR_CONFIG_TDP_CONTROL 0x0000064B
-#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
-
/* Hardware P state interface */
#define MSR_PPERF 0x0000064e
#define MSR_PERF_LIMIT_REASONS 0x0000064f
--
2.5.0
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| From | Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> |
|---|---|
| Date | 2016-03-28 22:10 +0200 |
| Subject | Re: [PATCH] x86: cpufreq: remove duplicated TDP MSR macro definitions |
| Message-ID | <rhLE6-3x9-5@gated-at.bofh.it> |
| In reply to | #1364973 |
On Sat, 2016-03-26 at 20:47 +0200, Vladimir Zapolskiy wrote:
> The list of CPU model specific registers contains two copies of TDP
> registers, remove the one, which is out of numerical order in the
> list.
>
Thanks for finding this.
> Fixes: 6a35fc2d6c22 ("cpufreq: intel_pstate: get P1 from TAR when
> available")
> Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> ---
> arch/x86/include/asm/msr-index.h | 8 +-------
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 2da46ac..426e946 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -190,6 +190,7 @@
> #define MSR_PP1_ENERGY_STATUS 0x00000641
> #define MSR_PP1_POLICY 0x00000642
>
> +/* Config TDP MSRs */
> #define MSR_CONFIG_TDP_NOMINAL 0x00000648
> #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
> #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
> @@ -210,13 +211,6 @@
> #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
> #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
>
> -/* Config TDP MSRs */
> -#define MSR_CONFIG_TDP_NOMINAL 0x00000648
> -#define MSR_CONFIG_TDP_LEVEL1 0x00000649
> -#define MSR_CONFIG_TDP_LEVEL2 0x0000064A
> -#define MSR_CONFIG_TDP_CONTROL 0x0000064B
> -#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
> -
> /* Hardware P state interface */
> #define MSR_PPERF 0x0000064e
> #define MSR_PERF_LIMIT_REASONS 0x0000064f
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| From | tip-bot for Vladimir Zapolskiy <tipbot@zytor.com> |
|---|---|
| Date | 2016-03-29 11:20 +0200 |
| Subject | [tip:x86/urgent] x86/cpufreq: Remove duplicated TDP MSR macro definitions |
| Message-ID | <rhXYC-3S8-9@gated-at.bofh.it> |
| In reply to | #1364973 |
Commit-ID: 4a6772f514891eaacf26bcb7c2c808c557d23c6f
Gitweb: http://git.kernel.org/tip/4a6772f514891eaacf26bcb7c2c808c557d23c6f
Author: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
AuthorDate: Sat, 26 Mar 2016 20:47:00 +0200
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Tue, 29 Mar 2016 11:12:10 +0200
x86/cpufreq: Remove duplicated TDP MSR macro definitions
The list of CPU model specific registers contains two copies of TDP
registers, remove the one, which is out of numerical order in the
list.
Fixes: 6a35fc2d6c22 ("cpufreq: intel_pstate: get P1 from TAR when available")
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Cc: Len Brown <len.brown@intel.com>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Cc: Kristen Carlson
Accardi <kristen@linux.intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: http://lkml.kernel.org/r/1459018020-24577-1-git-send-email-vladimir_zapolskiy@mentor.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/msr-index.h | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 2da46ac..426e946 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -190,6 +190,7 @@
#define MSR_PP1_ENERGY_STATUS 0x00000641
#define MSR_PP1_POLICY 0x00000642
+/* Config TDP MSRs */
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
@@ -210,13 +211,6 @@
#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
-/* Config TDP MSRs */
-#define MSR_CONFIG_TDP_NOMINAL 0x00000648
-#define MSR_CONFIG_TDP_LEVEL1 0x00000649
-#define MSR_CONFIG_TDP_LEVEL2 0x0000064A
-#define MSR_CONFIG_TDP_CONTROL 0x0000064B
-#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
-
/* Hardware P state interface */
#define MSR_PPERF 0x0000064e
#define MSR_PERF_LIMIT_REASONS 0x0000064f
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