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[PATCH v6 0/3] Add more clock compatible features and support the RK3399 clock

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  [PATCH v6 0/3] Add more clock compatible features and support the RK3399 clock Xing Zheng <zhengxing@rock-chips.com> - 2016-03-28 12:00 +0200
    [PATCH v6 1/3] dt-bindings: add bindings for rk3399 clock controller Xing Zheng <zhengxing@rock-chips.com> - 2016-03-28 12:00 +0200
    Re: [PATCH v6 0/3] Add more clock compatible features and support the RK3399 clock Heiko Stübner <heiko@sntech.de> - 2016-03-28 15:10 +0200
      Re: [PATCH v6 0/3] Add more clock compatible features and support the  RK3399 clock Xing Zheng <zhengxing@rock-chips.com> - 2016-03-29 03:20 +0200

#1365414 — [PATCH v6 0/3] Add more clock compatible features and support the RK3399 clock

Hi,
  The patch series add support more mux parameters and multiple
clock providers for the rockchip features of the clock framework,
and support the clock controller for the RK3399.


Changes in v6:
- update some clock contents
- fix the source of the pclkin_isp1_wrapper should be pclkin_cif
- remove unused the GRF reference in the clock driver
- use the frac mux type for spdif and i2s
- remove useless defines RK3399_PMU_RSTNHOLD_CON and RK3399_PMU_GATEDIS_CON

Changes in v5:
- add some necessary clock IDs
- keep PPLL independent into the part of the PMUCRU
- fix PMUCRU IDs are out of range
- add clock IDs to drivers reference
- fix some important bugs
- fix configuration for cpu tables

Changes in v3:
- rename pclkin_cif to pclkin_cifmux, add diagram and comment for
  pclkin_cifmux
- add the clk_test node
- modify the cif_testout path
- include two new patches that dt-bindings and header file from
  Jianqun's patch series

Changes in v2:
- rename the aplll/apllb to lpll/bpll
- add drv/sample clock nodes for sdmmc/sdio

Xing Zheng (3):
  dt-bindings: add bindings for rk3399 clock controller
  clk: rockchip: add dt-binding header for rk3399
  clk: rockchip: add clock controller for the RK3399

 .../bindings/clock/rockchip,rk3399-cru.txt         |   68 +
 drivers/clk/rockchip/Makefile                      |    1 +
 drivers/clk/rockchip/clk-rk3399.c                  | 1540 ++++++++++++++++++++
 drivers/clk/rockchip/clk.h                         |   22 +-
 include/dt-bindings/clock/rk3399-cru.h             |  752 ++++++++++
 5 files changed, 2382 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
 create mode 100644 drivers/clk/rockchip/clk-rk3399.c
 create mode 100644 include/dt-bindings/clock/rk3399-cru.h

-- 
1.7.9.5

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#1365415 — [PATCH v6 1/3] dt-bindings: add bindings for rk3399 clock controller

Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---

Changes in v6:
- update some clock contents

Changes in v5: None
Changes in v3: None
Changes in v2: None

 .../bindings/clock/rockchip,rk3399-cru.txt         |   68 ++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
new file mode 100644
index 0000000..bb2687d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,68 @@
+* Rockchip RK3399 Clock and Reset Unit
+
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "clkin_gmac" - external GMAC clock - optional,
+ - "gmac_phy_rx_clk" - external GMAC RX clock - optional,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "pclkin_cif" - external ISP clock - optional,
+ - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
+ - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
+
+Example: Clock controller node:
+
+	pmucru: pmu-clock-controller@ff750000 {
+		compatible = "rockchip,rk3399-pmucru";
+		reg = <0x0 0xff750000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	cru: clock-controller@ff760000 {
+		compatible = "rockchip,rk3399-cru";
+		reg = <0x0 0xff760000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+	uart0: serial@ff1a0000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff180000 0x0 0x100>;
+		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
-- 
1.7.9.5

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#1365479

Am Montag, 28. März 2016, 17:51:34 schrieb Xing Zheng:
>   The patch series add support more mux parameters and multiple
> clock providers for the rockchip features of the clock framework,
> and support the clock controller for the RK3399.

applied all 3 for 4.7 with one change:

I've dropped the grf paragraph from the binding doc (as it is not used 
anymore) and also dropped the gmac_phy_rx_clk input clock.

We can add these back once they are getting used in the future.


Heiko

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#1365760 — Re: [PATCH v6 0/3] Add more clock compatible features and support the RK3399 clock

On 2016年03月28日 20:59, Heiko Stübner wrote:
> Am Montag, 28. März 2016, 17:51:34 schrieb Xing Zheng:
>>    The patch series add support more mux parameters and multiple
>> clock providers for the rockchip features of the clock framework,
>> and support the clock controller for the RK3399.
> applied all 3 for 4.7 with one change:
>
> I've dropped the grf paragraph from the binding doc (as it is not used
> anymore) and also dropped the gmac_phy_rx_clk input clock.
>
> We can add these back once they are getting used in the future.
>
>
> Heiko
>
OK, thanks Heiko. :-)

-- 
- Xing Zheng

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