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Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

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  Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Alexander Stein <alexander.stein@systec-electronic.com> - 2016-03-23 10:20 +0100
    RE: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller  support Minghuan Lian <minghuan.lian@nxp.com> - 2016-03-23 12:10 +0100
    Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller  support Marc Zyngier <marc.zyngier@arm.com> - 2016-03-23 12:10 +0100
      Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Alexander Stein <alexander.stein@systec-electronic.com> - 2016-03-23 12:20 +0100
        Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller  support Marc Zyngier <marc.zyngier@arm.com> - 2016-03-23 12:40 +0100

#1363270 — Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
> Some kind of NXP Layerscape SoC provides a MSI
> implementation which uses two SCFG registers MSIIR and
> MSIR to support 32 MSI interrupts for each PCIe controller.
> The patch is to support it.
> 
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>

Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>

Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though:
> grep eth3 /proc/interrupts
> 
>  63:         49          0       MSI 134742016 Edge      eth3-rx-0
>  64:          3          0       MSI 134742017 Edge      eth3-tx-0
>  65:          4          0       MSI 134742018 Edge      eth3

Best regards,
Alexander

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#1363334 — RE: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

Hi Alexander,

Thanks for your test.

Number 134742016 is calculated by the following code

/**
 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
 * @dev:	Pointer to the PCI device
 * @desc:	Pointer to the msi descriptor
 *
 * The ID number is only used within the irqdomain.
 */
irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
					  struct msi_desc *desc)
{
	return (irq_hw_number_t)desc->msi_attrib.entry_nr |
		PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
		(pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
}

And this value is assigned to the hwirq in the function:
static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
				    struct msi_desc *desc)
{
	arg->desc = desc;
	arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
					       desc);
}


Thanks,
Minghuan

> -----Original Message-----
> From: Alexander Stein [mailto:alexander.stein@systec-electronic.com]
> Sent: Wednesday, March 23, 2016 5:18 PM
> To: linux-kernel@vger.kernel.org
> Cc: Minghuan Lian <minghuan.lian@nxp.com>;
> linux-arm-kernel@lists.infradead.org; Marc Zyngier <marc.zyngier@arm.com>;
> Thomas Gleixner <tglx@linutronix.de>; Jason Cooper
> <jason@lakedaemon.net>; Roy Zang <roy.zang@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; Stuart Yoder <stuart.yoder@nxp.com>; Yang-Leo Li
> <leoyang.li@nxp.com>
> Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller
> support
> 
> On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
> > Some kind of NXP Layerscape SoC provides a MSI
> > implementation which uses two SCFG registers MSIIR and
> > MSIR to support 32 MSI interrupts for each PCIe controller.
> > The patch is to support it.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> 
> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
> 
> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit
> strange though:
> > grep eth3 /proc/interrupts
> >
> >  63:         49          0       MSI 134742016 Edge
> eth3-rx-0
> >  64:          3          0       MSI 134742017 Edge
> eth3-tx-0
> >  65:          4          0       MSI 134742018 Edge      eth3
> 
> Best regards,
> Alexander

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#1363340 — Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

On 23/03/16 09:18, Alexander Stein wrote:
> On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> 
> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
> 
> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though:
>> grep eth3 /proc/interrupts
>>
>>  63:         49          0       MSI 134742016 Edge      eth3-rx-0
>>  64:          3          0       MSI 134742017 Edge      eth3-tx-0
>>  65:          4          0       MSI 134742018 Edge      eth3

This is a virtual interrupt number (despite being displayed as a hwirq),
computed from the PCI requester ID and the MSI index. You shouldn't
infer anything from it.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

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#1363345

On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote:
> > Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though:
> >> grep eth3 /proc/interrupts
> >>
> >>  63:         49          0       MSI 134742016 Edge      eth3-rx-0
> >>  64:          3          0       MSI 134742017 Edge      eth3-tx-0
> >>  65:          4          0       MSI 134742018 Edge      eth3
> 
> This is a virtual interrupt number (despite being displayed as a hwirq),
> computed from the PCI requester ID and the MSI index. You shouldn't
> infer anything from it.

Why show it anyway then if you can't infer anything?

Best regards,
Alexander

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#1363360 — Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

On 23/03/16 11:19, Alexander Stein wrote:
> On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote:
>>> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though:
>>>> grep eth3 /proc/interrupts
>>>>
>>>>  63:         49          0       MSI 134742016 Edge      eth3-rx-0
>>>>  64:          3          0       MSI 134742017 Edge      eth3-tx-0
>>>>  65:          4          0       MSI 134742018 Edge      eth3
>>
>> This is a virtual interrupt number (despite being displayed as a hwirq),
>> computed from the PCI requester ID and the MSI index. You shouldn't
>> infer anything from it.
> 
> Why show it anyway then if you can't infer anything?

Because this field conveys meaningful information for almost every other
interrupt in the system. I'm not going to special case the MSI layer
just on the ground that it may not be always useful (and in fact it *is*
useful if you know what the generating function is).

	M.
-- 
Jazz is not dead. It just smells funny...

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