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Groups > linux.kernel > #1354758 > unrolled thread

[PATCH 00/18] ARM: vf610: Suspend/resume with self-refresh mode

Started byStefan Agner <stefan@agner.ch>
First post2016-03-10 03:20 +0100
Last post2016-03-10 03:30 +0100
Articles 14 — 3 participants

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Contents

  [PATCH 00/18] ARM: vf610: Suspend/resume with self-refresh mode Stefan Agner <stefan@agner.ch> - 2016-03-10 03:20 +0100
    [PATCH 02/18] ARM: dts: vf610: add GPC as new interrupt parent Stefan Agner <stefan@agner.ch> - 2016-03-10 03:20 +0100
    [PATCH 11/18] pinctrl: pinctrl-imx: implement suspend/resume Stefan Agner <stefan@agner.ch> - 2016-03-10 03:20 +0100
    [PATCH 07/18] ARM: imx: clk-vf610: leave DDR clock on Stefan Agner <stefan@agner.ch> - 2016-03-10 03:20 +0100
    [PATCH 16/18] ARM: vf610: PM: enable Suspend-to-RAM only if hardware fixes are in place Stefan Agner <stefan@agner.ch> - 2016-03-10 03:20 +0100
    [PATCH 15/18] ARM: vf610: PM: initial suspend/resume support Stefan Agner <stefan@agner.ch> - 2016-03-10 03:20 +0100
      Re: [PATCH 15/18] ARM: vf610: PM: initial suspend/resume support kbuild test robot <lkp@intel.com> - 2016-03-10 22:30 +0100
    [PATCH 05/18] ARM: dts: vf610: add modules required for PM Stefan Agner <stefan@agner.ch> - 2016-03-10 03:30 +0100
    [PATCH 06/18] ARM: imx: clk-gate2: allow custom gate configuration Stefan Agner <stefan@agner.ch> - 2016-03-10 03:30 +0100
    [PATCH 10/18] tty: serial: fsl_lpuart: support suspend/resume Stefan Agner <stefan@agner.ch> - 2016-03-10 03:30 +0100
    [PATCH 04/18] ARM: dts: vf610: add on-chip SRAM Stefan Agner <stefan@agner.ch> - 2016-03-10 03:30 +0100
    [PATCH 08/18] ARM: clk: add WKPU unit Stefan Agner <stefan@agner.ch> - 2016-03-10 03:30 +0100
      Re: [PATCH 08/18] ARM: clk: add WKPU unit Stephen Boyd <sboyd@codeaurora.org> - 2016-03-16 02:20 +0100
    [PATCH 03/18] ARM: dts: vf610-colibri: GPIO wakeup key Stefan Agner <stefan@agner.ch> - 2016-03-10 03:30 +0100

#1354758 — [PATCH 00/18] ARM: vf610: Suspend/resume with self-refresh mode

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:20 +0100
Subject[PATCH 00/18] ARM: vf610: Suspend/resume with self-refresh mode
Message-ID<raYmJ-aJ-9@gated-at.bofh.it>
This is a reworked and extended respin of an older patchset posted
back in 2014:
http://lkml.iu.edu/hypermail/linux/kernel/1409.2/03734.html

This implementation supports Vybrids STOP (standby) and LPSTOP2
mode (mem). Only the latter puts the memory in self-refresh mode
and the SoC in a deep sleep state. However, self-refresh is only
supported if external pull-ups/downs are populated (which not
all hardware revisions have in place), therefor this patchset also
introduces a device tree property to denote whether memory can be
put into self-refresh mode or not.

The LPSTOP2 implementation is similar to the i.MX 6 implementation:
Entering and resuming from self-refresh mode is implemented in
assembler, and the function is copied to SRAM while entering suspend
mode.

There are several fixes and extensions necessary to make suspend
actually working, mainly because most blocks loose its state in
LPSTOP2 mode.

Feedback welcome! Especially the linking between the GPIOs of the 
WKPU unit (which allows to use some GPIOs as wake-up source) and
the regular GPIO block seems rather hacky...

The code has been tested on a Colibri VF50 and VF61. Currently
there is an issue with USB Host not correctly restoring after
resume which could not yet been resolved.

Stefan Agner (18):
  irqchip: vf610-gpc: add Vybrid GPC IRQ controller
  ARM: dts: vf610: add GPC as new interrupt parent
  ARM: dts: vf610-colibri: GPIO wakeup key
  ARM: dts: vf610: add on-chip SRAM
  ARM: dts: vf610: add modules required for PM
  ARM: imx: clk-gate2: allow custom gate configuration
  ARM: imx: clk-vf610: leave DDR clock on
  ARM: clk: add WKPU unit
  ARM: vf610: clk: add suspend/resume support
  tty: serial: fsl_lpuart: support suspend/resume
  pinctrl: pinctrl-imx: implement suspend/resume
  gpio: vf610: add system PM suspend/resume
  ARM: dts: vf610: add WKPU connection to GPIO
  gpio: vf610: add support for WKPU unit
  ARM: vf610: PM: initial suspend/resume support
  ARM: vf610: PM: enable Suspend-to-RAM only if hardware fixes are in
    place
  Documentation: dt: add Vybrid DDR memory controller bindings
  ARM: vf610: PM: enable SNVS access

 .../bindings/arm/freescale/fsl,vf610-ddrmc.txt     |  23 +
 .../devicetree/bindings/gpio/gpio-vf610.txt        |   6 +
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi          |  22 +
 arch/arm/boot/dts/vfxxx.dtsi                       |  74 ++-
 arch/arm/mach-imx/Makefile                         |   3 +
 arch/arm/mach-imx/common.h                         |  10 +
 arch/arm/mach-imx/mach-vf610.c                     |   8 +
 arch/arm/mach-imx/pm-vf610.c                       | 649 +++++++++++++++++++++
 arch/arm/mach-imx/suspend-vf610.S                  | 448 ++++++++++++++
 drivers/clk/imx/clk-gate2.c                        |   7 +-
 drivers/clk/imx/clk-vf610.c                        |  83 ++-
 drivers/clk/imx/clk.h                              |  13 +-
 drivers/gpio/gpio-vf610.c                          | 188 ++++++
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-vf610-gpc.c                    | 138 +++++
 drivers/pinctrl/freescale/pinctrl-imx.c            |  63 ++
 drivers/pinctrl/freescale/pinctrl-imx.h            |   3 +
 drivers/pinctrl/freescale/pinctrl-vf610.c          |   6 +
 drivers/tty/serial/fsl_lpuart.c                    |  16 +-
 include/dt-bindings/clock/vf610-clock.h            |   4 +-
 20 files changed, 1750 insertions(+), 15 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt
 create mode 100644 arch/arm/mach-imx/pm-vf610.c
 create mode 100644 arch/arm/mach-imx/suspend-vf610.S
 create mode 100644 drivers/irqchip/irq-vf610-gpc.c

-- 
2.7.2

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#1354759 — [PATCH 02/18] ARM: dts: vf610: add GPC as new interrupt parent

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:20 +0100
Subject[PATCH 02/18] ARM: dts: vf610: add GPC as new interrupt parent
Message-ID<raYmK-aJ-27@gated-at.bofh.it>
In reply to#1354758
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vfxxx.dtsi | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 5e49fbd..909988d 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -88,7 +88,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
-		interrupt-parent = <&mscm_ir>;
+		interrupt-parent = <&gpc>;
 		ranges;
 
 		aips0: aips-bus@40000000 {
@@ -475,6 +475,14 @@
 				reg = <0x4006e000 0x1000>;
 				interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
 			};
+
+			gpc: gpc@4006c000 {
+				compatible = "fsl,vf610-gpc";
+				reg = <0x4006c000 0x1000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&mscm_ir>;
+			};
 		};
 
 		aips1: aips-bus@40080000 {
-- 
2.7.2

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#1354760 — [PATCH 11/18] pinctrl: pinctrl-imx: implement suspend/resume

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:20 +0100
Subject[PATCH 11/18] pinctrl: pinctrl-imx: implement suspend/resume
Message-ID<raYmK-aJ-25@gated-at.bofh.it>
In reply to#1354758
In some SoC's using the IMX pin controller, the IP looses its state
when entering lowest power modes. Enhance the driver with suspend/
resume functions restoring the pin states.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/pinctrl/freescale/pinctrl-imx.c   | 63 +++++++++++++++++++++++++++++++
 drivers/pinctrl/freescale/pinctrl-imx.h   |  3 ++
 drivers/pinctrl/freescale/pinctrl-vf610.c |  6 +++
 3 files changed, 72 insertions(+)

diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index a5bb939..42fc9a9 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -24,6 +24,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/slab.h>
+#include <linux/syscore_ops.h>
 
 #include "../core.h"
 #include "pinctrl-imx.h"
@@ -42,6 +43,8 @@ struct imx_pinctrl {
 	void __iomem *base;
 	void __iomem *input_sel_base;
 	const struct imx_pinctrl_soc_info *info;
+	u32 *mux_regs;
+	u32 *input_regs;
 };
 
 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
@@ -689,6 +692,54 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 	return 0;
 }
 
+static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
+{
+	struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
+	int i;
+
+	for (i = 0; i < info->npins; i++) {
+		const struct imx_pin_reg *pin_reg = &info->pin_regs[i];
+
+		if (pin_reg->mux_reg == -1)
+			continue;
+
+		ipctl->mux_regs[i] = readl(ipctl->base + pin_reg->mux_reg);
+	}
+
+	for (i = 0; i < info->ninput_regs; i++)
+		ipctl->input_regs[i] = readl(ipctl->base +
+				info->input_regs_offset + i * sizeof(u32 *));
+
+	return 0;
+}
+
+static int __maybe_unused imx_pinctrl_resume(struct device *dev)
+{
+	struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
+	const struct imx_pin_reg *pin_reg;
+	int i;
+
+	for (i = 0; i < info->npins; i++) {
+		pin_reg = &info->pin_regs[i];
+		if (pin_reg->mux_reg == -1)
+			continue;
+
+		writel(ipctl->mux_regs[i], ipctl->base + pin_reg->mux_reg);
+	}
+
+	for (i = 0; i < info->ninput_regs; i++)
+		writel(ipctl->input_regs[i], ipctl->base +
+				info->input_regs_offset + i * sizeof(u32 *));
+
+	return 0;
+}
+
+const struct dev_pm_ops imx_pinctrl_dev_pm_ops = {
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, imx_pinctrl_resume)
+};
+
 int imx_pinctrl_probe(struct platform_device *pdev,
 		      struct imx_pinctrl_soc_info *info)
 {
@@ -719,6 +770,18 @@ int imx_pinctrl_probe(struct platform_device *pdev,
 		info->pin_regs[i].conf_reg = -1;
 	}
 
+#ifdef CONFIG_PM_SLEEP
+	ipctl->mux_regs = devm_kzalloc(&pdev->dev, sizeof(u32 *) *
+				       info->npins, GFP_KERNEL);
+	if (!ipctl->mux_regs)
+		return -ENOMEM;
+
+	ipctl->input_regs = devm_kzalloc(&pdev->dev, sizeof(u32 *) *
+					 info->ninput_regs, GFP_KERNEL);
+	if (!ipctl->input_regs)
+		return -ENOMEM;
+#endif
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(ipctl->base))
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 2a592f6..56851a6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -81,6 +81,8 @@ struct imx_pinctrl_soc_info {
 	unsigned int group_index;
 	struct imx_pmx_func *functions;
 	unsigned int nfunctions;
+	unsigned int input_regs_offset;
+	unsigned int ninput_regs;
 	unsigned int flags;
 };
 
@@ -99,4 +101,5 @@ struct imx_pinctrl_soc_info {
 int imx_pinctrl_probe(struct platform_device *pdev,
 			struct imx_pinctrl_soc_info *info);
 int imx_pinctrl_remove(struct platform_device *pdev);
+extern const struct dev_pm_ops imx_pinctrl_dev_pm_ops;
 #endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index 587d1ff..b6280a8 100644
--- a/drivers/pinctrl/freescale/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -19,6 +19,9 @@
 
 #include "pinctrl-imx.h"
 
+#define VF610_INPUT_REG_CNT		49
+#define VF610_INPUT_REG_BASE		0x2ec
+
 enum vf610_pads {
 	VF610_PAD_PTA6 = 0,
 	VF610_PAD_PTA8 = 1,
@@ -299,6 +302,8 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
 static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
 	.pins = vf610_pinctrl_pads,
 	.npins = ARRAY_SIZE(vf610_pinctrl_pads),
+	.input_regs_offset = VF610_INPUT_REG_BASE,
+	.ninput_regs = VF610_INPUT_REG_CNT,
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
 };
 
@@ -316,6 +321,7 @@ static struct platform_driver vf610_pinctrl_driver = {
 	.driver = {
 		.name = "vf610-pinctrl",
 		.of_match_table = vf610_pinctrl_of_match,
+		.pm = &imx_pinctrl_dev_pm_ops,
 	},
 	.probe = vf610_pinctrl_probe,
 	.remove = imx_pinctrl_remove,
-- 
2.7.2

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#1354762 — [PATCH 07/18] ARM: imx: clk-vf610: leave DDR clock on

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:20 +0100
Subject[PATCH 07/18] ARM: imx: clk-vf610: leave DDR clock on
Message-ID<raYmK-aJ-35@gated-at.bofh.it>
In reply to#1354758
To use STOP mode without putting DDR3 into self-refresh mode, we
need to keep the DDR clock enabled. Use the new gate configuration
with a value of 2 to make sure that the clock is enabled in RUN,
WAIT and STOP mode.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-vf610.c             | 3 +++
 include/dt-bindings/clock/vf610-clock.h | 3 ++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 0a94d96..f0ff458 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -119,6 +119,7 @@ static unsigned int const clks_init_on[] __initconst = {
 	VF610_CLK_SYS_BUS,
 	VF610_CLK_DDR_SEL,
 	VF610_CLK_DAP,
+	VF610_CLK_DDRMC,
 };
 
 static struct clk * __init vf610_get_fixed_clock(
@@ -233,6 +234,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 	clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock);
 	clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1);
 
+	clk[VF610_CLK_DDRMC] = imx_clk_gate2_cgr("ddrmc", "ddr_sel", CCM_CCGR6, CCM_CCGRx_CGn(14), 0x2);
+
 	clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6);
 	clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6);
 
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 56c16aa..cf2c00a 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -195,6 +195,7 @@
 #define VF610_CLK_SNVS			182
 #define VF610_CLK_DAP			183
 #define VF610_CLK_OCOTP         184
-#define VF610_CLK_END			185
+#define VF610_CLK_DDRMC			185
+#define VF610_CLK_END			186
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
-- 
2.7.2

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#1354763 — [PATCH 16/18] ARM: vf610: PM: enable Suspend-to-RAM only if hardware fixes are in place

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:20 +0100
Subject[PATCH 16/18] ARM: vf610: PM: enable Suspend-to-RAM only if hardware fixes are in place
Message-ID<raYmK-aJ-37@gated-at.bofh.it>
In reply to#1354758
To use self-refresh mode for DDR3 SDRAM memory in LPSTOPx mode, the
hardware need to have pull-ups/downs populated on RESET/CKE line of
the DDR memory. Read the device tree property which indicates whether
a given board has such resistors populated.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/mach-imx/pm-vf610.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/pm-vf610.c b/arch/arm/mach-imx/pm-vf610.c
index ecc7c9c..3da93e9 100644
--- a/arch/arm/mach-imx/pm-vf610.c
+++ b/arch/arm/mach-imx/pm-vf610.c
@@ -93,6 +93,7 @@
 
 static void __iomem *suspend_ocram_base;
 static void (*vf610_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+static bool has_cke_reset_pulls;
 
 #ifdef DEBUG
 static void __iomem *uart_membase;
@@ -382,7 +383,8 @@ static int vf610_pm_enter(suspend_state_t state)
 
 static int vf610_pm_valid(suspend_state_t state)
 {
-	return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
+	return (state == PM_SUSPEND_STANDBY ||
+		(state == PM_SUSPEND_MEM && has_cke_reset_pulls));
 }
 
 static const struct platform_suspend_ops vf610_pm_ops = {
@@ -476,6 +478,19 @@ static int __init vf610_suspend_init(const struct vf610_pm_socdata *socdata)
 		return ret;
 #endif
 
+	node = of_find_compatible_node(NULL, NULL, socdata->ddrmc_compat);
+	if (node) {
+		has_cke_reset_pulls =
+			of_property_read_bool(node, "fsl,has-cke-reset-pulls");
+
+		of_node_put(node);
+	}
+
+	if (has_cke_reset_pulls)
+		pr_info("PM: CKE/RESET pulls available, enable Suspend-to-RAM\n");
+	else
+		pr_info("PM: No CKE/RESET pulls, disable Suspend-to-RAM\n");
+
 	suspend_set_ops(&vf610_pm_ops);
 
 	node = of_find_compatible_node(NULL, NULL, "mmio-sram");
-- 
2.7.2

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#1354764 — [PATCH 15/18] ARM: vf610: PM: initial suspend/resume support

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:20 +0100
Subject[PATCH 15/18] ARM: vf610: PM: initial suspend/resume support
Message-ID<raYmK-aJ-33@gated-at.bofh.it>
In reply to#1354758
Add system suspend and resume support for Vybrid SoC. The standby
sleep state puts the SoC in STOP mode. The SoC can be woken through
an interrupt from GPC (Global Power Controller). The GPC can use any
interrupt as wake-up source. To save power the main PLL1 is bypassed
and uses the 24MHz on-chip oscillator. However, memory clock need to
be at full speed, hence the PLL2 needs to be on to keep the memory
clocked. The mode is completely implemented in C since we can access
the full memory at all times. The mode provides most power saving
while being able to be woken by any IRQ as wake-up source.

The mem sleep state (Suspend-to-RAM) uses Vybrid's LPSTOP2 mode. This
mode powergates most parts of the SoC expect some peripherials such as
Wake-Up controller (WKPU) or LP RTC. Parts of the internal SRAM is
retained too. The suspend code written in assembly runs from this SRAM.
The code puts the main memory (DDR3) into self-refresh mode and takes
it out of self-refresh mode on resume. Verified with Colibri VF50/VF61
V1.2A.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/mach-imx/Makefile        |   3 +
 arch/arm/mach-imx/common.h        |  10 +
 arch/arm/mach-imx/mach-vf610.c    |   8 +
 arch/arm/mach-imx/pm-vf610.c      | 634 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/suspend-vf610.S | 437 ++++++++++++++++++++++++++
 drivers/clk/imx/clk-vf610.c       |  17 +
 6 files changed, 1109 insertions(+)
 create mode 100644 arch/arm/mach-imx/pm-vf610.c
 create mode 100644 arch/arm/mach-imx/suspend-vf610.S

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9fbe624..ea2e8bd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -90,8 +90,11 @@ ifeq ($(CONFIG_SUSPEND),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
 obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
+AFLAGS_suspend-vf610.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SOC_VF610) += suspend-vf610.o
 endif
 obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
+obj-$(CONFIG_SOC_VF610) += pm-vf610.o
 
 obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
 obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 58a3846..737b1e4 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -76,6 +76,13 @@ enum mxc_cpu_pwr_mode {
 	STOP_POWER_OFF,		/* STOP + SRPG */
 };
 
+enum vf610_cpu_pwr_mode {
+	VF610_RUN,
+	VF610_LP_RUN,
+	VF610_STOP,
+	VF610_LP_STOP,
+};
+
 enum mx3_cpu_pwr_mode {
 	MX3_RUN,
 	MX3_WAIT,
@@ -120,11 +127,13 @@ void v7_cpu_resume(void);
 void imx53_suspend(void __iomem *ocram_vbase);
 extern const u32 imx53_suspend_sz;
 void imx6_suspend(void __iomem *ocram_vbase);
+void vf610_suspend(void __iomem *ocram_vbase);
 #else
 static inline void v7_cpu_resume(void) {}
 static inline void imx53_suspend(void __iomem *ocram_vbase) {}
 static const u32 imx53_suspend_sz;
 static inline void imx6_suspend(void __iomem *ocram_vbase) {}
+static inline void vf610_suspend(void __iomem *ocram_vbase) {}
 #endif
 
 void imx6_pm_ccm_init(const char *ccm_compat);
@@ -133,6 +142,7 @@ void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
 void imx6sx_pm_init(void);
 void imx6ul_pm_init(void);
+void vf610_pm_init(void);
 
 #ifdef CONFIG_PM
 void imx51_pm_init(void);
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index b20f6c1..5ba668f 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -11,6 +11,13 @@
 #include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "common.h"
+
+static void __init vf610_init_machine(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	vf610_pm_init();
+}
 
 static const char * const vf610_dt_compat[] __initconst = {
 	"fsl,vf500",
@@ -24,5 +31,6 @@ static const char * const vf610_dt_compat[] __initconst = {
 DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)")
 	.l2c_aux_val	= 0,
 	.l2c_aux_mask	= ~0,
+	.init_machine	= vf610_init_machine,
 	.dt_compat	= vf610_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-imx/pm-vf610.c b/arch/arm/mach-imx/pm-vf610.c
new file mode 100644
index 0000000..ecc7c9c
--- /dev/null
+++ b/arch/arm/mach-imx/pm-vf610.c
@@ -0,0 +1,634 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2016 Toradex AG
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifdef DEBUG
+#define pr_pmdebug(fmt, ...) pr_info("PM: VF610: " fmt "\n", ##__VA_ARGS__)
+#else
+#define pr_pmdebug(fmt, ...)
+#endif
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/genalloc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/suspend.h>
+#include <linux/clk.h>
+#include <asm/cacheflush.h>
+#include <asm/fncpy.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/tlb.h>
+
+#include "common.h"
+
+#define DDRMC_PHY_OFFSET		0x400
+
+#define CCR				0x0
+#define BM_CCR_FIRC_EN			(0x1 << 16)
+#define BM_CCR_FXOSC_EN			(0x1 << 12)
+
+#define CCSR				0x8
+#define BM_CCSR_DDRC_CLK_SEL		(0x1 << 6)
+#define BM_CCSR_FAST_CLK_SEL		(0x1 << 5)
+#define BM_CCSR_SLOW_CLK_SEL		(0x1 << 4)
+#define BM_CCSR_SYS_CLK_SEL_MASK	(0x7 << 0)
+
+#define CACRR				0xc
+
+#define CLPCR				0x2c
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
+#define BM_CLPCR_SBYOS			(0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC		(0x1 << 7)
+#define BM_CLPCR_ANADIG_STOP_MODE	(0x1 << 8)
+#define BM_CLPCR_FXOSC_BYPSEN		(0x1 << 10)
+#define BM_CLPCR_FXOSC_PWRDWN		(0x1 << 11)
+#define BM_CLPCR_MASK_CORE0_WFI		(0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI		(0x1 << 23)
+#define BM_CLPCR_MASK_SCU_IDLE		(0x1 << 24)
+#define BM_CLPCR_MASK_L2CC_IDLE		(0x1 << 25)
+
+#define CGPR				0x64
+#define BM_CGPR_INT_MEM_CLK_LPM		(0x1 << 17)
+
+#define GPC_PGCR			0x0
+#define BM_PGCR_DS_STOP			(0x1 << 7)
+#define BM_PGCR_DS_LPSTOP		(0x1 << 6)
+#define BM_PGCR_WB_STOP			(0x1 << 4)
+#define BM_PGCR_HP_OFF			(0x1 << 3)
+#define BM_PGCR_PG_PD1			(0x1 << 0)
+
+#define GPC_LPMR			0x40
+#define BM_LPMR_RUN			0x0
+#define BM_LPMR_STOP			0x2
+
+#define ANATOP_PLL1_CTRL		0x270
+#define ANATOP_PLL2_CTRL		0x30
+#define ANATOP_PLL2_PFD			0x100
+#define BM_PLL_POWERDOWN	(0x1 << 12)
+#define BM_PLL_ENABLE		(0x1 << 13)
+#define BM_PLL_BYPASS		(0x1 << 16)
+#define BM_PLL_LOCK		(0x1 << 31)
+#define BM_PLL_PFD2_CLKGATE	(0x1 << 15)
+#define BM_PLL_USB_POWER	(0x1 << 12)
+#define BM_PLL_EN_USB_CLKS	(0x1 << 6)
+
+#define VF610_DDRMC_IO_NUM		94
+#define VF610_IOMUX_DDR_IO_NUM		48
+#define VF610_ANATOP_IO_NUM		2
+
+static void __iomem *suspend_ocram_base;
+static void (*vf610_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+
+#ifdef DEBUG
+static void __iomem *uart_membase;
+static unsigned long uart_clk;
+#endif
+
+static const u32 vf610_iomuxc_ddr_io_offset[] __initconst = {
+	0x220, 0x224, 0x228, 0x22c, 0x230, 0x234, 0x238, 0x23c,
+	0x240, 0x244, 0x248, 0x24c, 0x250, 0x254, 0x258, 0x25c,
+	0x260, 0x264, 0x268, 0x26c, 0x270, 0x274, 0x278, 0x27c,
+	0x280, 0x284, 0x288, 0x28c, 0x290, 0x294, 0x298, 0x29c,
+	0x2a0, 0x2a4, 0x2a8, 0x2ac, 0x2b0, 0x2b4, 0x2b8, 0x2bc,
+	0x2c0, 0x2c4, 0x2c8, 0x2cc, 0x2d0, 0x2d4, 0x2d8, 0x21c,
+};
+
+
+static const u32 vf610_ddrmc_io_offset[] __initconst = {
+	0x00, 0x08, 0x28, 0x2c, 0x30, 0x34, 0x38,
+	0x40, 0x44, 0x48, 0x50, 0x54, 0x58, 0x5c,
+	0x60, 0x64, 0x68, 0x70, 0x74, 0x78, 0x7c,
+	0x84, 0x88, 0x98, 0x9c, 0xa4, 0xc0,
+	0x108, 0x10c, 0x114, 0x118, 0x120, 0x124,
+	0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c,
+	0x148, 0x15c, 0x160, 0x164, 0x16c, 0x180,
+	0x184, 0x188, 0x18c, 0x198, 0x1a4, 0x1a8,
+	0x1b8, 0x1d4, 0x1d8, 0x1e0, 0x1e4, 0x1e8,
+	0x1ec, 0x1f0, 0x1f8, 0x210, 0x224, 0x228,
+	0x22c, 0x230, 0x23c, 0x240, 0x244, 0x248,
+	0x24c, 0x250, 0x25c, 0x268, 0x26c, 0x278,
+	0x268
+};
+
+static const u32 vf610_ddrmc_phy_io_offset[] __initconst = {
+	0x00, 0x04, 0x08, 0x0c, 0x10,
+	0x40, 0x44, 0x48, 0x4c, 0x50,
+	0x80, 0x84, 0x88, 0x8c, 0x90,
+	0xc4, 0xc8, 0xd0
+};
+
+/*
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      vf610_suspend code
+ *              PM_INFO structure(vf610_cpu_pm_info)
+ * ======================== low address =======================
+ */
+
+struct vf610_pm_base {
+	phys_addr_t pbase;
+	void __iomem *vbase;
+};
+
+struct vf610_pm_socdata {
+	const char *anatop_compat;
+	const char *scsc_compat;
+	const char *wkpu_compat;
+	const char *ccm_compat;
+	const char *gpc_compat;
+	const char *src_compat;
+	const char *ddrmc_compat;
+	const char *iomuxc_compat;
+};
+
+static const struct vf610_pm_socdata vf610_pm_data __initconst = {
+	.anatop_compat = "fsl,vf610-anatop",
+	.scsc_compat = "fsl,vf610-scsc",
+	.wkpu_compat = "fsl,vf610-wkpu",
+	.ccm_compat = "fsl,vf610-ccm",
+	.gpc_compat = "fsl,vf610-gpc",
+	.src_compat = "fsl,vf610-src",
+	.ddrmc_compat = "fsl,vf610-ddrmc",
+	.iomuxc_compat = "fsl,vf610-iomuxc",
+};
+
+/*
+ * This structure is for passing necessary data for low level ocram
+ * suspend code(arch/arm/mach-imx/suspend-vf610.S), if this struct
+ * definition is changed, the offset definition in
+ * arch/arm/mach-imx/suspend-vf610.S must be also changed accordingly,
+ * otherwise, the suspend to ocram function will be broken!
+ */
+struct vf610_cpu_pm_info {
+	phys_addr_t pbase; /* The physical address of pm_info. */
+	phys_addr_t resume_addr; /* The physical resume address for asm code */
+	u32 cpu_type; /* Currently not used, leave it for alignment */
+	u32 pm_info_size; /* Size of pm_info. */
+	struct vf610_pm_base anatop_base;
+	struct vf610_pm_base scsc_base;
+	struct vf610_pm_base wkpu_base;
+	struct vf610_pm_base ccm_base;
+	struct vf610_pm_base gpc_base;
+	struct vf610_pm_base src_base;
+	struct vf610_pm_base ddrmc_base;
+	struct vf610_pm_base iomuxc_base;
+	struct vf610_pm_base l2_base;
+	u32 ccm_cacrr;
+	u32 ccm_ccsr;
+	u32 ddrmc_io_num; /* Number of MMDC IOs which need saved/restored. */
+	u32 ddrmc_io_val[VF610_DDRMC_IO_NUM][2]; /* To save offset and value */
+	u32 iomux_ddr_io_num;
+	u32 iomux_ddr_io_val[VF610_IOMUX_DDR_IO_NUM][2];
+} __aligned(8);
+
+#ifdef DEBUG
+static void vf610_uart_reinit(unsigned long int rate, unsigned long int baud)
+{
+	u8 tmp, c2;
+	u16 sbr, brfa;
+
+	/* UART_C2 */
+	c2 = __raw_readb(uart_membase + 0x3);
+	__raw_writeb(0, uart_membase + 0x3);
+
+	sbr = (u16) (rate / (baud * 16));
+	brfa = (rate / baud) - (sbr * 16);
+
+	tmp = ((sbr & 0x1f00) >> 8);
+	__raw_writeb(tmp, uart_membase + 0x0);
+	tmp = sbr & 0x00ff;
+	__raw_writeb(tmp, uart_membase + 0x1);
+
+	/* UART_C4 */
+	__raw_writeb(brfa & 0xf, uart_membase + 0xa);
+
+	__raw_writeb(c2, uart_membase + 0x3);
+}
+#else
+#define vf610_uart_reinit(rate, baud)
+#endif
+
+static void vf610_set(void __iomem *pll_base, u32 mask)
+{
+	writel(readl(pll_base) | mask, pll_base);
+}
+
+static void vf610_clr(void __iomem *pll_base, u32 mask)
+{
+	writel(readl(pll_base) & ~mask, pll_base);
+}
+
+int vf610_set_lpm(enum vf610_cpu_pwr_mode mode)
+{
+	struct vf610_cpu_pm_info *pm_info = suspend_ocram_base;
+	void __iomem *ccm_base = pm_info->ccm_base.vbase;
+	void __iomem *gpc_base = pm_info->gpc_base.vbase;
+	void __iomem *anatop = pm_info->anatop_base.vbase;
+	u32 ccr = readl_relaxed(ccm_base + CCR);
+	u32 ccsr = readl_relaxed(ccm_base + CCSR);
+	u32 cacrr = readl_relaxed(ccm_base + CACRR);
+	u32 cclpcr = 0;
+	u32 gpc_pgcr = 0;
+
+	switch (mode) {
+	case VF610_LP_STOP:
+		/* Store clock settings */
+		pm_info->ccm_ccsr = ccsr;
+		pm_info->ccm_cacrr = cacrr;
+
+		ccr |= BM_CCR_FIRC_EN;
+		writel_relaxed(ccr, ccm_base + CCR);
+
+		cclpcr |= BM_CLPCR_ANADIG_STOP_MODE;
+		cclpcr |= BM_CLPCR_SBYOS;
+
+		cclpcr |= BM_CLPCR_MASK_SCU_IDLE;
+		cclpcr |= BM_CLPCR_MASK_L2CC_IDLE;
+		cclpcr |= BM_CLPCR_MASK_CORE1_WFI;
+		writel_relaxed(cclpcr, ccm_base + CLPCR);
+
+		gpc_pgcr |= BM_PGCR_DS_STOP;
+		gpc_pgcr |= BM_PGCR_DS_LPSTOP;
+		gpc_pgcr |= BM_PGCR_WB_STOP;
+		gpc_pgcr |= BM_PGCR_HP_OFF;
+		gpc_pgcr |= BM_PGCR_PG_PD1;
+		writel_relaxed(gpc_pgcr, gpc_base + GPC_PGCR);
+		break;
+	case VF610_STOP:
+		cclpcr &= ~BM_CLPCR_ANADIG_STOP_MODE;
+		cclpcr |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+		cclpcr |= BM_CLPCR_SBYOS;
+		writel_relaxed(cclpcr, ccm_base + CLPCR);
+
+		gpc_pgcr |= BM_PGCR_DS_STOP;
+		gpc_pgcr |= BM_PGCR_HP_OFF;
+		writel_relaxed(gpc_pgcr, gpc_base + GPC_PGCR);
+
+		/* fall-through */
+	case VF610_LP_RUN:
+		/* Store clock settings */
+		pm_info->ccm_ccsr = ccsr;
+		pm_info->ccm_cacrr = cacrr;
+
+		ccr |= BM_CCR_FIRC_EN;
+		writel_relaxed(ccr, ccm_base + CCR);
+
+		/* Enable PLL2 for DDR clock */
+		vf610_set(anatop + ANATOP_PLL2_CTRL, BM_PLL_ENABLE);
+		vf610_clr(anatop + ANATOP_PLL2_CTRL, BM_PLL_POWERDOWN);
+		vf610_clr(anatop + ANATOP_PLL2_CTRL, BM_PLL_BYPASS);
+		while (!(readl(anatop + ANATOP_PLL2_CTRL) & BM_PLL_LOCK));
+		vf610_clr(anatop + ANATOP_PLL2_PFD, BM_PLL_PFD2_CLKGATE);
+
+		/* Switch internal OSC's */
+		ccsr &= ~BM_CCSR_FAST_CLK_SEL;
+		ccsr &= ~BM_CCSR_SLOW_CLK_SEL;
+
+		/* Select PLL2 as DDR clock */
+		ccsr &= ~BM_CCSR_DDRC_CLK_SEL;
+		writel_relaxed(ccsr, ccm_base + CCSR);
+
+		ccsr &= ~BM_CCSR_SYS_CLK_SEL_MASK;
+		writel_relaxed(ccsr, ccm_base + CCSR);
+		vf610_uart_reinit(4000000UL, 115200);
+
+		vf610_set(anatop + ANATOP_PLL1_CTRL, BM_PLL_BYPASS);
+		writel_relaxed(BM_LPMR_STOP, gpc_base + GPC_LPMR);
+		break;
+	case VF610_RUN:
+		writel_relaxed(BM_LPMR_RUN, gpc_base + GPC_LPMR);
+
+		vf610_clr(anatop + ANATOP_PLL1_CTRL, BM_PLL_BYPASS);
+		while (!(readl(anatop + ANATOP_PLL1_CTRL) & BM_PLL_LOCK));
+
+		/* Restore clock settings */
+		writel(pm_info->ccm_ccsr, ccm_base + CCSR);
+
+		vf610_uart_reinit(uart_clk, 115200);
+		pr_pmdebug("resuming, uart_reinit done");
+
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int vf610_suspend_finish(unsigned long val)
+{
+	if (!vf610_suspend_in_ocram_fn) {
+		cpu_do_idle();
+	} else {
+		/*
+		 * call low level suspend function in ocram,
+		 * as we need to float DDR IO.
+		 */
+		local_flush_tlb_all();
+		flush_cache_all();
+		outer_flush_all();
+		vf610_suspend_in_ocram_fn(suspend_ocram_base);
+	}
+
+	return 0;
+}
+
+static int vf610_pm_enter(suspend_state_t state)
+{
+	switch (state) {
+	case PM_SUSPEND_STANDBY:
+		vf610_set_lpm(VF610_STOP);
+
+		/* zzZZZzzz */
+		cpu_do_idle();
+
+		vf610_set_lpm(VF610_RUN);
+		break;
+	case PM_SUSPEND_MEM:
+		vf610_set_lpm(VF610_LP_STOP);
+
+		cpu_suspend(0, vf610_suspend_finish);
+		outer_resume();
+
+		vf610_set_lpm(VF610_RUN);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int vf610_pm_valid(suspend_state_t state)
+{
+	return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
+}
+
+static const struct platform_suspend_ops vf610_pm_ops = {
+	.enter = vf610_pm_enter,
+	.valid = vf610_pm_valid,
+};
+
+static int __init imx_pm_get_base(struct vf610_pm_base *base,
+				const char *compat)
+{
+	struct device_node *node;
+	struct resource res;
+	int ret = 0;
+
+	node = of_find_compatible_node(NULL, NULL, compat);
+	if (!node) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	ret = of_address_to_resource(node, 0, &res);
+	if (ret)
+		goto put_node;
+
+	base->pbase = res.start;
+	base->vbase = ioremap(res.start, resource_size(&res));
+
+	if (!base->vbase)
+		ret = -ENOMEM;
+
+put_node:
+	of_node_put(node);
+out:
+	return ret;
+}
+
+#ifdef DEBUG
+static int __init vf610_uart_init(void)
+{
+	struct device_node *dn;
+	const char *name;
+	struct clk *clk;
+	int ret;
+
+	name = of_get_property(of_chosen, "stdout-path", NULL);
+	if (name == NULL)
+		return -ENODEV;
+
+	dn = of_find_node_by_path(name);
+	if (!dn)
+		return -ENODEV;
+
+	clk = of_clk_get(dn, 0);
+
+	if (!clk) {
+		ret = PTR_ERR(clk);
+		goto put_node;
+	}
+
+	uart_clk = clk_get_rate(clk);
+
+	uart_membase = of_iomap(dn, 0);
+	if (!clk) {
+		ret = -ENOMEM;
+		goto put_node;
+	}
+
+	ret = 0;
+
+put_node:
+	of_node_put(dn);
+	return ret;
+}
+#endif
+
+static int __init vf610_suspend_init(const struct vf610_pm_socdata *socdata)
+{
+	phys_addr_t ocram_pbase;
+	struct device_node *node;
+	struct platform_device *pdev;
+	struct vf610_cpu_pm_info *pm_info;
+	struct gen_pool *ocram_pool;
+	size_t ocram_size;
+	unsigned long ocram_base;
+	int ret = 0, reg = 0;
+	int i;
+
+#ifdef DEBUG
+	ret = vf610_uart_init();
+	if (ret < 0)
+		return ret;
+#endif
+
+	suspend_set_ops(&vf610_pm_ops);
+
+	node = of_find_compatible_node(NULL, NULL, "mmio-sram");
+	if (!node) {
+		pr_warn("%s: failed to find ocram node!\n", __func__);
+		return -ENODEV;
+	}
+
+	pdev = of_find_device_by_node(node);
+	if (!pdev) {
+		pr_warn("%s: failed to find ocram device!\n", __func__);
+		ret = -ENODEV;
+		goto put_node;
+	}
+
+	ocram_pool = gen_pool_get(&pdev->dev, "stbyram1");
+	if (!ocram_pool) {
+		pr_warn("%s: ocram pool unavailable!\n", __func__);
+		ret = -ENODEV;
+		goto put_node;
+	}
+
+	ocram_size = gen_pool_size(ocram_pool);
+	ocram_base = gen_pool_alloc(ocram_pool, ocram_size);
+	if (!ocram_base) {
+		pr_warn("%s: unable to alloc ocram!\n", __func__);
+		ret = -ENOMEM;
+		goto put_node;
+	}
+
+	ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
+
+	suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, ocram_size, false);
+
+	pm_info = suspend_ocram_base;
+	pm_info->pbase = ocram_pbase;
+	pm_info->resume_addr = virt_to_phys(cpu_resume);
+	pm_info->pm_info_size = sizeof(*pm_info);
+
+	ret = imx_pm_get_base(&pm_info->anatop_base, socdata->anatop_compat);
+	if (ret) {
+		pr_warn("%s: failed to get anatop base %d!\n", __func__, ret);
+		goto put_node;
+	}
+
+	ret = imx_pm_get_base(&pm_info->scsc_base, socdata->scsc_compat);
+	if (ret) {
+		pr_warn("%s: failed to get scsc base %d!\n", __func__, ret);
+		goto scsc_map_failed;
+	}
+
+	ret = imx_pm_get_base(&pm_info->ccm_base, socdata->ccm_compat);
+	if (ret) {
+		pr_warn("%s: failed to get ccm base %d!\n", __func__, ret);
+		goto ccm_map_failed;
+	}
+
+	ret = imx_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
+	if (ret) {
+		pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
+		goto gpc_map_failed;
+	}
+
+	ret = imx_pm_get_base(&pm_info->src_base, socdata->src_compat);
+	if (ret) {
+		pr_warn("%s: failed to get src base %d!\n", __func__, ret);
+		goto src_map_failed;
+	}
+
+	ret = imx_pm_get_base(&pm_info->ddrmc_base, socdata->ddrmc_compat);
+	if (ret) {
+		pr_warn("%s: failed to get ddrmc base %d!\n", __func__, ret);
+		goto ddrmc_map_failed;
+	}
+
+	ret = imx_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
+	if (ret) {
+		pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
+		goto iomuxc_map_failed;
+	}
+
+	ret = imx_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
+	if (ret == -ENODEV)
+		ret = 0;
+	if (ret) {
+		pr_warn("%s: failed to get pl310-cache base %d!\n",
+			__func__, ret);
+		goto pl310_cache_map_failed;
+	}
+
+	pm_info->ddrmc_io_num = VF610_DDRMC_IO_NUM;
+
+	/* Store DDRMC registers */
+	for (i = 0; i < ARRAY_SIZE(vf610_ddrmc_io_offset); i++, reg++) {
+		pm_info->ddrmc_io_val[reg][0] = vf610_ddrmc_io_offset[i];
+		pm_info->ddrmc_io_val[reg][1] =
+			readl_relaxed(pm_info->ddrmc_base.vbase +
+			vf610_ddrmc_io_offset[i]);
+	}
+
+	/* Store DDRMC PHY registers */
+	for (i = 0; i < ARRAY_SIZE(vf610_ddrmc_phy_io_offset); i++, reg++) {
+		pm_info->ddrmc_io_val[reg][0] = vf610_ddrmc_phy_io_offset[i] +
+			DDRMC_PHY_OFFSET;
+		pm_info->ddrmc_io_val[reg][1] =
+			readl_relaxed(pm_info->ddrmc_base.vbase +
+			DDRMC_PHY_OFFSET + vf610_ddrmc_phy_io_offset[i]);
+	}
+
+	/* Store IOMUX DDR pad registers */
+	pm_info->iomux_ddr_io_num = VF610_IOMUX_DDR_IO_NUM;
+	for (i = 0; i < ARRAY_SIZE(vf610_iomuxc_ddr_io_offset); i++) {
+		pm_info->iomux_ddr_io_val[i][0] = vf610_iomuxc_ddr_io_offset[i];
+		pm_info->iomux_ddr_io_val[i][1] =
+			readl_relaxed(pm_info->iomuxc_base.vbase +
+			vf610_iomuxc_ddr_io_offset[i]);
+	}
+
+	vf610_suspend_in_ocram_fn = fncpy(
+		suspend_ocram_base + sizeof(*pm_info),
+		&vf610_suspend, ocram_size - sizeof(*pm_info));
+
+	goto put_node;
+
+pl310_cache_map_failed:
+	iounmap(pm_info->iomuxc_base.vbase);
+iomuxc_map_failed:
+	iounmap(pm_info->ddrmc_base.vbase);
+ddrmc_map_failed:
+	iounmap(pm_info->src_base.vbase);
+src_map_failed:
+	iounmap(pm_info->gpc_base.vbase);
+gpc_map_failed:
+	iounmap(pm_info->ccm_base.vbase);
+ccm_map_failed:
+	iounmap(pm_info->scsc_base.vbase);
+scsc_map_failed:
+	iounmap(pm_info->anatop_base.vbase);
+put_node:
+	of_node_put(node);
+
+	return ret;
+}
+
+void __init vf610_pm_init(void)
+{
+	int ret;
+
+	if (IS_ENABLED(CONFIG_SUSPEND)) {
+		ret = vf610_suspend_init(&vf610_pm_data);
+		if (ret)
+			pr_warn("%s: No DDR LPM support with suspend %d!\n",
+				__func__, ret);
+	}
+}
+
diff --git a/arch/arm/mach-imx/suspend-vf610.S b/arch/arm/mach-imx/suspend-vf610.S
new file mode 100644
index 0000000..09ad246
--- /dev/null
+++ b/arch/arm/mach-imx/suspend-vf610.S
@@ -0,0 +1,437 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2016 Toradex AG
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+
+/*
+ * ==================== low level suspend ====================
+ *
+ * Better to follow below rules to use ARM registers:
+ * r0: pm_info structure address;
+ * r1 ~ r4: for saving pm_info members;
+ * r5 ~ r10: free registers;
+ * r11: io base address.
+ *
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      vf610_suspend code
+ *              PM_INFO structure(vf610_cpu_pm_info)
+ * ======================== low address =======================
+ */
+
+/*
+ * Below offsets are based on struct vf610_cpu_pm_info
+ * which defined in arch/arm/mach-imx/pm-vf610.c, this
+ * structure contains necessary pm info for low level
+ * suspend related code.
+ */
+#define PM_INFO_PBASE_OFFSET			0x0
+#define PM_INFO_RESUME_ADDR_OFFSET		0x4
+#define PM_INFO_CPU_TYPE_OFFSET			0x8
+#define PM_INFO_PM_INFO_SIZE_OFFSET		0xC
+#define PM_INFO_VF610_ANATOP_P_OFFSET		0x10
+#define PM_INFO_VF610_ANATOP_V_OFFSET		0x14
+#define PM_INFO_VF610_SCSC_P_OFFSET		0x18
+#define PM_INFO_VF610_SCSC_V_OFFSET		0x1C
+#define PM_INFO_VF610_WKPU_P_OFFSET		0x20
+#define PM_INFO_VF610_WKPU_V_OFFSET		0x24
+#define PM_INFO_VF610_CCM_P_OFFSET		0x28
+#define PM_INFO_VF610_CCM_V_OFFSET		0x2C
+#define PM_INFO_VF610_GPC_P_OFFSET		0x30
+#define PM_INFO_VF610_GPC_V_OFFSET		0x34
+#define PM_INFO_VF610_SRC_P_OFFSET		0x38
+#define PM_INFO_VF610_SRC_V_OFFSET		0x3C
+#define PM_INFO_VF610_DDRMC_P_OFFSET		0x40
+#define PM_INFO_VF610_DDRMC_V_OFFSET		0x44
+#define PM_INFO_VF610_IOMUXC_P_OFFSET		0x48
+#define PM_INFO_VF610_IOMUXC_V_OFFSET		0x4c
+#define PM_INFO_VF610_L2_P_OFFSET		0x50
+#define PM_INFO_VF610_L2_V_OFFSET		0x54
+#define PM_INFO_CCM_CACRR			0x58
+#define PM_INFO_CCM_CCSR			0x5c
+#define PM_INFO_DDRMC_IO_NUM_OFFSET		0x60
+#define PM_INFO_DDRMC_IO_VAL_OFFSET		0x64
+#define PM_INFO_IOMUXC_DDR_IO_NUM_OFFSET	(0x64 + 94 * 2 * 4)
+#define PM_INFO_IOMUXC_DDR_IO_VAL_OFFSET	(0x68 + 94 * 2 * 4)
+
+#define VF610_ANADIG_PLL2_CTRL			0x30
+
+#define VF610_ANADIG_MISC0			0x150
+#define VF610_ANADIG_MISC0_CLK_24M_IRC_XTAL_SEL	(0x1 < 13)
+
+#define VF610_ANADIG_PLL1_CTRL			0x270
+
+#define VF610_ANADIG_POWERDOWN			(1 << 12)
+#define VF610_ANADIG_ENABLE			(1 << 13)
+#define VF610_ANADIG_BYPASS			(1 << 16)
+#define VF610_ANADIG_LOCK			(1 << 31)
+
+#define VF610_SCSC_SIRC				0x0
+#define VF610_SCSC_SIRC_SIRC_EN			(0x1 << 0)
+#define VF610_SCSC_SOSC				0x4
+#define VF610_SCSC_SOSC_SOSC_EN			(0x1 << 0)
+
+#define VF610_GPC_PGCR				0x0
+#define VF610_GPC_LPMR				0x40
+
+#define VF610_CCM_CCR				0x00
+#define VF610_CCM_CCR_FXOSC_EN			(0x1 << 12)
+
+#define VF610_CCM_CCSR				0x08
+#define VF610_CCM_CCSR_DDRC_CLK_SEL		(0x1 << 6)
+#define VF610_CCM_CCSR_FAST_CLK_SEL		(0x1 << 5)
+
+#define VF610_CCM_CACRR				0x0C
+
+#define VF610_CCM_CLPCR				0x2C
+#define VF610_CCM_CLPCR_DIS_REF_OSC		(0x1 << 7)
+#define VF610_CCM_CLPCR_FXOSC_PWRDWN		(0x1 << 11)
+
+#define VF610_CCM_CCGR0				0x40
+#define VF610_CCM_CCGR2				0x48
+#define VF610_CCM_CCGR3				0x4C
+#define VF610_CCM_CCGR4				0x50
+#define VF610_CCM_CCGR6				0x58
+
+#define VF610_SRC_GPR0				0x20
+#define VF610_SRC_GPR1				0x24
+#define VF610_SRC_MISC2				0x54
+
+#define VF610_DDRMC_CR00			0x0
+#define VF610_DDRMC_CR00_START			(0x1 << 0)
+
+#define VF610_DDRMC_CR33			0x84
+#define VF610_DDRMC_CR33_PWUP_SREF_EX		(0x1 << 0)
+
+#define VF610_DDRMC_CR34			0x88
+
+#define VF610_DDRMC_CR35			0x8C
+#define VF610_DDRMC_CR35_LP_CMD(cmd)		((cmd) << 8)
+
+#define VF610_DDRMC_CR80			0x140
+#define VF610_DDRMC_CR80_LP_COMPLETE		(0x1 << 9)
+#define VF610_DDRMC_CR80_INIT_COMPLETE		(0x1 << 8)
+#define VF610_DDRMC_CR81			0x144
+
+	.align 3
+
+	/*
+	 * Take DDR RAM out of Low-Power mode
+	 */
+	.macro resume_ddrmc ddrmc_base
+
+	/* Clear low power complete flag... */
+	ldr	r6, =VF610_DDRMC_CR80_LP_COMPLETE
+	str	r6, [\ddrmc_base, #VF610_DDRMC_CR81]
+
+	ldr	r6, [\ddrmc_base, #VF610_DDRMC_CR35]
+	orr	r6, r6, #VF610_DDRMC_CR35_LP_CMD(0x9)
+	str	r6, [\ddrmc_base, #VF610_DDRMC_CR35]
+
+1:
+	ldr	r5, [\ddrmc_base, #VF610_DDRMC_CR80]
+	ands 	r5, r5, #VF610_DDRMC_CR80_LP_COMPLETE
+	beq	1b
+
+	.endm
+
+	.macro enable_syspll pll_base
+
+	ldr	r5, [\pll_base]
+	orr	r5, r5, #VF610_ANADIG_ENABLE
+	bic	r5, r5, #VF610_ANADIG_POWERDOWN
+	bic	r5, r5, #VF610_ANADIG_BYPASS
+	str	r5, [\pll_base]
+
+1:
+	ldr	r5, [\pll_base]
+	tst 	r5, #VF610_ANADIG_LOCK
+	beq	1b
+
+	.endm
+
+ENTRY(vf610_suspend)
+	ldr	r1, [r0, #PM_INFO_PBASE_OFFSET]
+	ldr	r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+	ldr	r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+	ldr	r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
+
+	/*
+	 * make sure TLB contain the addr we want,
+	 * as we will access them after DDRMC IO floated.
+	 */
+
+	ldr	r11, [r0, #PM_INFO_VF610_DDRMC_V_OFFSET]
+	ldr	r6, [r11, #0x0]
+	ldr	r11, [r0, #PM_INFO_VF610_GPC_V_OFFSET]
+	ldr	r6, [r11, #0x0]
+	ldr	r11, [r0, #PM_INFO_VF610_SRC_V_OFFSET]
+	ldr	r6, [r11, #0x0]
+	ldr	r11, [r0, #PM_INFO_VF610_CCM_V_OFFSET]
+	ldr	r6, [r11, #0x0]
+
+	ldr	r11, [r0, #PM_INFO_VF610_SRC_V_OFFSET]
+
+	/* Disable DDR RESET */
+	ldr	r6, [r11, #VF610_SRC_MISC2]
+	orr	r6, r6, #0x1
+	str	r6, [r11, #VF610_SRC_MISC2]
+
+	/* Set ENTRY/ARGUMENT register */
+	ldr	r6, =vf610_suspend
+	ldr	r7, =resume
+	sub	r7, r7, r6
+	add	r8, r1, r4
+	add	r9, r8, r7
+	str	r9, [r11, #VF610_SRC_GPR0]
+	str	r1, [r11, #VF610_SRC_GPR1]
+
+	/* Put memory in self refresh... */
+	ldr	r11, [r0, #PM_INFO_VF610_DDRMC_V_OFFSET]
+
+	ldr	r6, =VF610_DDRMC_CR80_LP_COMPLETE
+	str	r6, [r11, #VF610_DDRMC_CR81]
+
+	ldr	r6, [r11, #VF610_DDRMC_CR35]
+	orr	r6, r6, #VF610_DDRMC_CR35_LP_CMD(0xA)
+	str	r6, [r11, #VF610_DDRMC_CR35]
+
+ddrmc_cmd_complete:
+	/* Hardware without CKE/RESET fixes seems to hang at this read.... */
+	ldr	r5, [r11, #VF610_DDRMC_CR80]
+	ands 	r5, r5, #VF610_DDRMC_CR80_LP_COMPLETE
+	beq	ddrmc_cmd_complete
+
+	/* switch to internal FIRC */
+	ldr	r11, [r0, #PM_INFO_VF610_CCM_V_OFFSET]
+	ldr	r5, [r11, #VF610_CCM_CCSR]
+	bic	r5, r5, #0x30 /* FAST_/SLOW_CLK_SEL */
+	str	r5, [r11, #VF610_CCM_CCSR]
+	bic	r5, r5, #0x07 /* SYS_CLK_SEL */
+	str	r5, [r11, #VF610_CCM_CCSR]
+
+	/* LP-Mode: STOP */
+	ldr	r11, [r0, #PM_INFO_VF610_GPC_V_OFFSET]
+	ldr	r6, =0x02
+	str	r6, [r11, #VF610_GPC_LPMR]
+
+	/* Zzz, enter stop mode */
+	wfi
+	nop
+	nop
+	nop
+	nop
+
+	/* If we get here, there is already an interrupt pending. Restore... */
+	ldr	r6, =0x00
+	str	r6, [r11, #VF610_GPC_LPMR]
+
+	/* Get previous CCSR/CACRR settings */
+	ldr	r11, [r0, #PM_INFO_VF610_CCM_V_OFFSET]
+	ldr	r5, [r0, #PM_INFO_CCM_CCSR]
+	str	r5, [r11, #VF610_CCM_CCSR]
+
+	ldr	r5, [r0, #PM_INFO_CCM_CACRR]
+	str	r5, [r11, #VF610_CCM_CACRR]
+
+	ldr	r11, [r0, #PM_INFO_VF610_DDRMC_V_OFFSET]
+	resume_ddrmc r11
+
+	ret	lr
+
+/* Resume path if CPU uses the SRC_GPR0 (PERSISTENT_ENTRY0) */
+resume:
+	/* invalidate L1 I-cache first */
+	mov     r6, #0x0
+	mcr     p15, 0, r6, c7, c5, 0
+	mcr     p15, 0, r6, c7, c5, 6
+
+	/* enable the Icache and branch prediction */
+	mov     r6, #0x1800
+	mcr     p15, 0, r6, c1, c0, 0
+	isb
+
+	ldr	r11, [r0, #PM_INFO_VF610_CCM_P_OFFSET]
+
+	ldr	r5, [r11, #VF610_CCM_CCSR]
+	orr	r5, r5, #(1 << 13)
+	str	r5, [r11, #VF610_CCM_CCSR]
+
+	/* enable IOMUX, PORT A-E */
+	ldr	r5, [r11, #VF610_CCM_CCGR2]
+	ldr	r6, =0xfff0000
+	orr	r5, r5, r6
+	str	r5, [r11, #VF610_CCM_CCGR2]
+
+	/* enable ANADIG and SCSM */
+	ldr	r5, [r11, #VF610_CCM_CCGR3]
+	orr	r5, r5, #0x33
+	str	r5, [r11, #VF610_CCM_CCGR3]
+
+	/* enable GPC, CCM and WKUP */
+	ldr	r5, [r11, #VF610_CCM_CCGR4]
+	orr	r5, r5, #0x3f00000
+	str	r5, [r11, #VF610_CCM_CCGR4]
+
+	/* enable DDRMC */
+	ldr	r5, [r11, #VF610_CCM_CCGR6]
+	orr	r5, r5, #0x30000000
+	str	r5, [r11, #VF610_CCM_CCGR6]
+
+#ifdef DEBUG
+	/* enable UART0 */
+	ldr	r5, [r11, #VF610_CCM_CCGR0]
+	orr	r5, r5, #0xC000
+	str	r5, [r11, #VF610_CCM_CCGR0]
+
+	/* Mux UART0 */
+	ldr	r5,=0x1021a2
+	ldr	r6,=0x40048080
+	str	r5, [r6, #0x0]
+	ldr	r5,=0x1021a1
+	ldr	r6,=0x40048084
+	str	r5, [r6, #0x0]
+#endif
+
+	/* Set IOMUX for DDR pads */
+	ldr	r11, [r0, #PM_INFO_VF610_IOMUXC_P_OFFSET]
+
+	ldr	r6, [r0, #PM_INFO_IOMUXC_DDR_IO_NUM_OFFSET]
+	ldr	r7, =PM_INFO_IOMUXC_DDR_IO_VAL_OFFSET
+	add	r7, r7, r0
+
+loop_iomuxc_ddr_restore:
+	ldr	r8, [r7], #0x4
+	ldr	r9, [r7], #0x4
+	str	r9, [r11, r8]
+	subs	r6, r6, #0x1
+	bne	loop_iomuxc_ddr_restore
+
+
+	/* Enable slow oscilators */
+	ldr	r11, [r0, #PM_INFO_VF610_SCSC_P_OFFSET]
+
+	ldr	r5, [r11, #VF610_SCSC_SOSC]
+	orr	r5, r5, #VF610_SCSC_SOSC_SOSC_EN
+	str	r5, [r11, #VF610_SCSC_SOSC]
+
+	ldr	r5, [r11, #VF610_SCSC_SIRC]
+	orr	r5, r5, #VF610_SCSC_SIRC_SIRC_EN
+	str	r5, [r11, #VF610_SCSC_SIRC]
+
+	/* Enable fast osciallator */
+	ldr	r11, [r0, #PM_INFO_VF610_CCM_P_OFFSET]
+
+	ldr	r5, [r11, #VF610_CCM_CLPCR]
+	bic	r5, r5, #VF610_CCM_CLPCR_DIS_REF_OSC
+	bic	r5, r5, #VF610_CCM_CLPCR_FXOSC_PWRDWN
+	str	r5, [r11, #VF610_CCM_CLPCR]
+
+	ldr	r5, [r11, #VF610_CCM_CCR]
+	orr	r5, r5, #VF610_CCM_CCR_FXOSC_EN
+	str	r5, [r11, #VF610_CCM_CCR]
+
+	ldr	r5, [r11, #VF610_CCM_CCSR]
+	orr	r5, r5, #VF610_CCM_CCSR_FAST_CLK_SEL
+	str	r5, [r11, #VF610_CCM_CCSR]
+
+	ldr	r11, [r0, #PM_INFO_VF610_ANATOP_P_OFFSET]
+
+	/* Select external FXOSC */
+	ldr	r5, [r11, #VF610_ANADIG_MISC0]
+	bic	r5, r5, #VF610_ANADIG_MISC0_CLK_24M_IRC_XTAL_SEL
+	str	r5, [r11, #VF610_ANADIG_MISC0]
+
+	add	r6, r11, #VF610_ANADIG_PLL1_CTRL
+	enable_syspll r6
+
+	/* enable pll2 only if required for DDR */
+	ldr	r5, [r0, #PM_INFO_CCM_CCSR]
+	tst 	r5, #VF610_CCM_CCSR_DDRC_CLK_SEL
+	bne	switch_sysclk
+
+	add	r6, r11, #VF610_ANADIG_PLL2_CTRL
+	enable_syspll r6
+
+switch_sysclk:
+
+	/* Enable PFD and switch to fast clock */
+	ldr	r11, [r0, #PM_INFO_VF610_CCM_P_OFFSET]
+
+	/* Get previous CCSR/CACRR settings */
+	ldr	r5, [r0, #PM_INFO_CCM_CCSR]
+	str	r5, [r11, #VF610_CCM_CCSR]
+
+	ldr	r5, [r0, #PM_INFO_CCM_CACRR]
+	str	r5, [r11, #VF610_CCM_CACRR]
+
+	/* Restore memory configuration */
+	ldr	r11, [r0, #PM_INFO_VF610_DDRMC_P_OFFSET]
+
+	ldr	r6, [r0, #PM_INFO_DDRMC_IO_NUM_OFFSET]
+	ldr	r7, =PM_INFO_DDRMC_IO_VAL_OFFSET
+	add	r7, r7, r0
+
+	/* Clear start bit of first memory register, do not start yet... */
+	ldr	r8, [r7], #0x4
+	ldr	r9, [r7], #0x4
+	bic	r9, r9, #VF610_DDRMC_CR00_START
+	str	r9, [r11, r8]
+	subs	r6, r6, #0x1
+
+loop_ddrmc_restore:
+	ldr	r8, [r7], #0x4
+	ldr	r9, [r7], #0x4
+	str	r9, [r11, r8]
+	subs	r6, r6, #0x1
+	bne	loop_ddrmc_restore
+
+	/* Set PWUP_SREF_EX to avoid a full memory initialization */
+	ldr	r6, [r11, #VF610_DDRMC_CR33]
+	orr	r6, r6, #VF610_DDRMC_CR33_PWUP_SREF_EX
+	str	r6, [r11, #VF610_DDRMC_CR33]
+
+	/* Start initialization */
+	ldr	r6, =VF610_DDRMC_CR80_INIT_COMPLETE
+	str	r6, [r11, #VF610_DDRMC_CR81]
+
+	ldr	r6, [r11, #VF610_DDRMC_CR00]
+	orr	r6, r6, #VF610_DDRMC_CR00_START
+	str	r6, [r11, #VF610_DDRMC_CR00]
+
+ddrmc_initializing:
+	ldr	r5, [r11, #VF610_DDRMC_CR80]
+	ands 	r5, r5, #VF610_DDRMC_CR80_INIT_COMPLETE
+	beq	ddrmc_initializing
+
+	resume_ddrmc r11
+
+	/* LP-Mode: RUN */
+	ldr	r11, [r0, #PM_INFO_VF610_GPC_P_OFFSET]
+	ldr	r5, =0x0
+	str	r5, [r11, #VF610_GPC_LPMR]
+
+	/* get physical resume address from pm_info. */
+	ldr	lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+
+	ret	lr
+ENDPROC(vf610_suspend)
+
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 170a96c..27d4cf0 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -117,6 +117,11 @@ static struct clk_div_table pll4_audio_div_table[] = {
 static struct clk *clk[VF610_CLK_END];
 static struct clk_onecell_data clk_data;
 
+static u32 anadig_pll3_ctrl;
+static u32 anadig_pll4_ctrl;
+static u32 anadig_pll5_ctrl;
+static u32 anadig_pll6_ctrl;
+static u32 anadig_pll7_ctrl;
 static u32 cscmr1;
 static u32 cscmr2;
 static u32 cscdr1;
@@ -147,6 +152,12 @@ static int vf610_clk_suspend(void)
 {
 	int i;
 
+	anadig_pll3_ctrl = readl_relaxed(PLL3_CTRL);
+	anadig_pll4_ctrl = readl_relaxed(PLL4_CTRL);
+	anadig_pll5_ctrl = readl_relaxed(PLL5_CTRL);
+	anadig_pll6_ctrl = readl_relaxed(PLL6_CTRL);
+	anadig_pll7_ctrl = readl_relaxed(PLL7_CTRL);
+
 	cscmr1 = readl_relaxed(CCM_CSCMR1);
 	cscmr2 = readl_relaxed(CCM_CSCMR2);
 
@@ -164,6 +175,12 @@ static void vf610_clk_resume(void)
 {
 	int i;
 
+	writel_relaxed(anadig_pll3_ctrl, PLL3_CTRL);
+	writel_relaxed(anadig_pll4_ctrl, PLL4_CTRL);
+	writel_relaxed(anadig_pll5_ctrl, PLL5_CTRL);
+	writel_relaxed(anadig_pll6_ctrl, PLL6_CTRL);
+	writel_relaxed(anadig_pll7_ctrl, PLL7_CTRL);
+
 	writel_relaxed(cscmr1, CCM_CSCMR1);
 	writel_relaxed(cscmr2, CCM_CSCMR2);
 
-- 
2.7.2

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#1355410 — Re: [PATCH 15/18] ARM: vf610: PM: initial suspend/resume support

Fromkbuild test robot <lkp@intel.com>
Date2016-03-10 22:30 +0100
SubjectRe: [PATCH 15/18] ARM: vf610: PM: initial suspend/resume support
Message-ID<rbgjE-4mm-5@gated-at.bofh.it>
In reply to#1354764

[Multipart message — attachments visible in raw view] — view raw

Hi Stefan,

[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on v4.5-rc7]
[cannot apply to next-20160310]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]

url:    https://github.com/0day-ci/linux/commits/Stefan-Agner/ARM-vf610-Suspend-resume-with-self-refresh-mode/20160310-102621
base:   https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: arm-vf610m4_defconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   arch/arm/mach-imx/pm-vf610.c: In function 'vf610_suspend_finish':
>> arch/arm/mach-imx/pm-vf610.c:348:3: error: implicit declaration of function 'local_flush_tlb_all' [-Werror=implicit-function-declaration]
      local_flush_tlb_all();
      ^
   cc1: some warnings being treated as errors

vim +/local_flush_tlb_all +348 arch/arm/mach-imx/pm-vf610.c

   342			cpu_do_idle();
   343		} else {
   344			/*
   345			 * call low level suspend function in ocram,
   346			 * as we need to float DDR IO.
   347			 */
 > 348			local_flush_tlb_all();
   349			flush_cache_all();
   350			outer_flush_all();
   351			vf610_suspend_in_ocram_fn(suspend_ocram_base);

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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#1354765 — [PATCH 05/18] ARM: dts: vf610: add modules required for PM

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:30 +0100
Subject[PATCH 05/18] ARM: dts: vf610: add modules required for PM
Message-ID<raYwp-fk-1@gated-at.bofh.it>
In reply to#1354758
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vfxxx.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index b038ea4..335f4e5 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -434,6 +434,11 @@
 				reg = <0x40050000 0x400>;
 			};
 
+			scsc: scsc@40052000 {
+				compatible = "fsl,vf610-scsc";
+				reg = <0x40052000 0x1000>;
+			};
+
 			usbphy0: usbphy@40050800 {
 				compatible = "fsl,vf610-usbphy";
 				reg = <0x40050800 0x400>;
@@ -480,6 +485,13 @@
 				status = "disabled";
 			};
 
+			wakeup: wkpu@4006a000 {
+				compatible = "fsl,vf610-wkpu";
+				reg = <0x4006a000 0x1000>;
+				interrupts = <92 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks VF610_CLK_WKPU>;
+			};
+
 			clks: ccm@4006b000 {
 				compatible = "fsl,vf610-ccm";
 				reg = <0x4006b000 0x1000>;
@@ -600,6 +612,13 @@
 				status = "disabled";
 			};
 
+			ddrmc: ddrmc@400ae000 {
+				compatible = "fsl,vf610-ddrmc";
+				reg = <0x400ae000 0x400>;
+				clocks = <&clks VF610_CLK_DDRMC>;
+				clock-names = "ddrc";
+			};
+
 			adc1: adc@400bb000 {
 				compatible = "fsl,vf610-adc";
 				reg = <0x400bb000 0x1000>;
-- 
2.7.2

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#1354769 — [PATCH 06/18] ARM: imx: clk-gate2: allow custom gate configuration

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:30 +0100
Subject[PATCH 06/18] ARM: imx: clk-gate2: allow custom gate configuration
Message-ID<raYwq-fk-13@gated-at.bofh.it>
In reply to#1354758
The 2-bit gates found i.MX and Vybrid SoC support different clock
configuration:

0b00: clk disabled
0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode
0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid)
0b11: clk enabled in RUN and WAIT mode

For some clocks, we might want to configure different behaviour,
e.g. a memory clock should be on even in STOP mode. Add a new
function imx_clk_gate2_cgr which allow to configure specific
gate values through the cgr_val parameter.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-gate2.c |  7 +++++--
 drivers/clk/imx/clk.h       | 13 ++++++++++---
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 8935bff..db44a19 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -31,6 +31,7 @@ struct clk_gate2 {
 	struct clk_hw hw;
 	void __iomem	*reg;
 	u8		bit_idx;
+	u8		cgr_val;
 	u8		flags;
 	spinlock_t	*lock;
 	unsigned int	*share_count;
@@ -50,7 +51,8 @@ static int clk_gate2_enable(struct clk_hw *hw)
 		goto out;
 
 	reg = readl(gate->reg);
-	reg |= 3 << gate->bit_idx;
+	reg &= ~(3 << gate->bit_idx);
+	reg |= gate->cgr_val << gate->bit_idx;
 	writel(reg, gate->reg);
 
 out:
@@ -125,7 +127,7 @@ static struct clk_ops clk_gate2_ops = {
 
 struct clk *clk_register_gate2(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
-		void __iomem *reg, u8 bit_idx,
+		void __iomem *reg, u8 bit_idx, u8 cgr_val,
 		u8 clk_gate2_flags, spinlock_t *lock,
 		unsigned int *share_count)
 {
@@ -140,6 +142,7 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
 	/* struct clk_gate2 assignments */
 	gate->reg = reg;
 	gate->bit_idx = bit_idx;
+	gate->cgr_val = cgr_val;
 	gate->flags = clk_gate2_flags;
 	gate->lock = lock;
 	gate->share_count = share_count;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index c94ac5c..9311755 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -41,7 +41,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 
 struct clk *clk_register_gate2(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
-		void __iomem *reg, u8 bit_idx,
+		void __iomem *reg, u8 bit_idx, u8 cgr_val,
 		u8 clk_gate_flags, spinlock_t *lock,
 		unsigned int *share_count);
 
@@ -55,7 +55,7 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
 	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
-			shift, 0, &imx_ccm_lock, NULL);
+			shift, 0x3, 0, &imx_ccm_lock, NULL);
 }
 
 static inline struct clk *imx_clk_gate2_shared(const char *name,
@@ -63,7 +63,14 @@ static inline struct clk *imx_clk_gate2_shared(const char *name,
 		unsigned int *share_count)
 {
 	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
-			shift, 0, &imx_ccm_lock, share_count);
+			shift, 0x3, 0, &imx_ccm_lock, share_count);
+}
+
+static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
+		void __iomem *reg, u8 shift, u8 cgr_val)
+{
+	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+			shift, cgr_val, 0, &imx_ccm_lock, NULL);
 }
 
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
-- 
2.7.2

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#1354771 — [PATCH 10/18] tty: serial: fsl_lpuart: support suspend/resume

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:30 +0100
Subject[PATCH 10/18] tty: serial: fsl_lpuart: support suspend/resume
Message-ID<raYwq-fk-19@gated-at.bofh.it>
In reply to#1354758
In order to allow wake support in STOP sleep mode, clocks are
needed. Use imx_clk_gate2_cgr to disable automatic clock gating
in low power mode STOP. This allows to enable wake by UART using:
echo enabled > /sys/class/tty/ttyLP0/power/wakeup

However, if wake is not enabled, the driver should disable the
clocks explicitly to save power.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-vf610.c     | 12 ++++++------
 drivers/tty/serial/fsl_lpuart.c | 16 ++++++++++++++--
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index e2e2c43..170a96c 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -315,12 +315,12 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 
 	clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
 
-	clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
-	clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
-	clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
-	clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
-	clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9));
-	clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10));
+	clk[VF610_CLK_UART0] = imx_clk_gate2_cgr("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7), 0x2);
+	clk[VF610_CLK_UART1] = imx_clk_gate2_cgr("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8), 0x2);
+	clk[VF610_CLK_UART2] = imx_clk_gate2_cgr("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9), 0x2);
+	clk[VF610_CLK_UART3] = imx_clk_gate2_cgr("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10), 0x2);
+	clk[VF610_CLK_UART4] = imx_clk_gate2_cgr("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9), 0x2);
+	clk[VF610_CLK_UART5] = imx_clk_gate2_cgr("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10), 0x2);
 
 	clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
 	clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 3d79003..94e29ba 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -483,9 +483,8 @@ static void lpuart_dma_rx_complete(void *arg)
 	spin_unlock_irqrestore(&sport->port.lock, flags);
 }
 
-static void lpuart_timer_func(unsigned long data)
+static void lpuart_dma_rx_terminate(struct lpuart_port *sport)
 {
-	struct lpuart_port *sport = (struct lpuart_port *)data;
 	struct tty_port *port = &sport->port.state->port;
 	struct dma_tx_state state;
 	unsigned long flags;
@@ -510,6 +509,11 @@ static void lpuart_timer_func(unsigned long data)
 	spin_unlock_irqrestore(&sport->port.lock, flags);
 }
 
+static void lpuart_timer_func(unsigned long data)
+{
+	lpuart_dma_rx_terminate((struct lpuart_port *)data);
+}
+
 static inline void lpuart_prepare_rx(struct lpuart_port *sport)
 {
 	unsigned long flags;
@@ -1915,7 +1919,12 @@ static int lpuart_suspend(struct device *dev)
 		writeb(temp, sport->port.membase + UARTCR2);
 	}
 
+	if (sport->dma_rx_in_progress)
+		lpuart_dma_rx_terminate(sport);
+
 	uart_suspend_port(&lpuart_reg, &sport->port);
+	if (sport->port.suspended && !sport->port.irq_wake)
+		clk_disable_unprepare(sport->clk);
 
 	return 0;
 }
@@ -1925,6 +1934,9 @@ static int lpuart_resume(struct device *dev)
 	struct lpuart_port *sport = dev_get_drvdata(dev);
 	unsigned long temp;
 
+	if (sport->port.suspended && !sport->port.irq_wake)
+		clk_prepare_enable(sport->clk);
+
 	if (sport->lpuart32) {
 		lpuart32_setup_watermark(sport);
 		temp = lpuart32_read(sport->port.membase + UARTCTRL);
-- 
2.7.2

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#1354775 — [PATCH 04/18] ARM: dts: vf610: add on-chip SRAM

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:30 +0100
Subject[PATCH 04/18] ARM: dts: vf610: add on-chip SRAM
Message-ID<raYwq-fk-25@gated-at.bofh.it>
In reply to#1354758
Add Vybrids massive on-chip SRAM areas. Make use of the memory
region functionality to denominate the retained SRAM area in
LPSTOP2 and LPSTOP3.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vfxxx.dtsi | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 909988d..b038ea4 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -91,6 +91,43 @@
 		interrupt-parent = <&gpc>;
 		ranges;
 
+		ocram0: sram@3f000000 {
+			compatible = "mmio-sram";
+			reg = <0x3f000000 0x40000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x3f000000 0x40000>;
+
+			stbyram1@0 {
+				reg = <0x0 0x4000>;
+				label = "stbyram1";
+				pool;
+			};
+
+			stbyram2@4000 {
+				reg = <0x4000 0xc000>;
+				label = "stbyram2";
+				pool;
+			};
+		};
+
+		ocram1: sram@3f040000 {
+			compatible = "mmio-sram";
+			reg = <0x3f040000 0x40000>;
+		};
+
+		gfxram0: sram@3f400000 {
+			compatible = "mmio-sram";
+			reg = <0x3f400000 0x80000>;
+		};
+
+		/* used by L2 cache */
+		gfxram1: sram@3f480000 {
+			compatible = "mmio-sram";
+			reg = <0x3f480000 0x80000>;
+		};
+
 		aips0: aips-bus@40000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
-- 
2.7.2

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#1354778 — [PATCH 08/18] ARM: clk: add WKPU unit

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:30 +0100
Subject[PATCH 08/18] ARM: clk: add WKPU unit
Message-ID<raYwq-fk-29@gated-at.bofh.it>
In reply to#1354758
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-vf610.c             | 2 ++
 include/dt-bindings/clock/vf610-clock.h | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index f0ff458..610a724 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -120,6 +120,7 @@ static unsigned int const clks_init_on[] __initconst = {
 	VF610_CLK_DDR_SEL,
 	VF610_CLK_DAP,
 	VF610_CLK_DDRMC,
+	VF610_CLK_WKPU,
 };
 
 static struct clk * __init vf610_get_fixed_clock(
@@ -235,6 +236,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 	clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1);
 
 	clk[VF610_CLK_DDRMC] = imx_clk_gate2_cgr("ddrmc", "ddr_sel", CCM_CCGR6, CCM_CCGRx_CGn(14), 0x2);
+	clk[VF610_CLK_WKPU] = imx_clk_gate2_cgr("wkpu", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(10), 0x2);
 
 	clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6);
 	clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6);
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index cf2c00a..7dc1b84 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -196,6 +196,7 @@
 #define VF610_CLK_DAP			183
 #define VF610_CLK_OCOTP         184
 #define VF610_CLK_DDRMC			185
-#define VF610_CLK_END			186
+#define VF610_CLK_WKPU			186
+#define VF610_CLK_END			187
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
-- 
2.7.2

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#1358461 — Re: [PATCH 08/18] ARM: clk: add WKPU unit

FromStephen Boyd <sboyd@codeaurora.org>
Date2016-03-16 02:20 +0100
SubjectRe: [PATCH 08/18] ARM: clk: add WKPU unit
Message-ID<rd8hX-1JP-1@gated-at.bofh.it>
In reply to#1354778
On 03/09, Stefan Agner wrote:
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1354781 — [PATCH 03/18] ARM: dts: vf610-colibri: GPIO wakeup key

FromStefan Agner <stefan@agner.ch>
Date2016-03-10 03:30 +0100
Subject[PATCH 03/18] ARM: dts: vf610-colibri: GPIO wakeup key
Message-ID<raYwr-fk-35@gated-at.bofh.it>
In reply to#1354758
Enable GPIO wakeup key on Vybrid PAD 41 which is routed to the
Colibri default wakeup pin SO-DIMM 45.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 4d8b7f6..936ece6 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -39,6 +39,8 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/input/input.h>
+
 / {
 	chosen {
 		stdout-path = "serial0:115200n8";
@@ -74,6 +76,20 @@
 		gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */
 		vin-supply = <&reg_5v0>;
 	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpiokeys>;
+
+		power {
+			label = "Wake-Up";
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_WAKEUP>;
+			debounce-interval = <10>;
+			gpio-key,wakeup;
+		};
+	};
 };
 
 &bl {
@@ -157,5 +173,11 @@
 				VF610_PAD_PTB21__GPIO_43	0x22ed
 			>;
 		};
+
+		pinctrl_gpiokeys: gpiokeys {
+			fsl,pins = <
+				VF610_PAD_PTB19__GPIO_41	0x218d
+			>;
+		};
 	};
 };
-- 
2.7.2

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