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[PATCH 00/10] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file

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  [PATCH 00/10] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi  file Chanwoo Choi <cw00.choi@samsung.com> - 2016-03-14 03:10 +0100
    [PATCH 01/10] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi <cw00.choi@samsung.com> - 2016-03-14 03:10 +0100
    [PATCH 02/10] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi <cw00.choi@samsung.com> - 2016-03-14 03:10 +0100
    [PATCH 03/10] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi <cw00.choi@samsung.com> - 2016-03-14 03:10 +0100
    [PATCH 10/10] ARM: dts: Add PPMU node for exynos3250-artik5 module Chanwoo Choi <cw00.choi@samsung.com> - 2016-03-14 03:10 +0100
      Re: [PATCH 10/10] ARM: dts: Add PPMU node for exynos3250-artik5 module Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-03-14 09:40 +0100
        Re: [PATCH 10/10] ARM: dts: Add PPMU node for exynos3250-artik5 module Chanwoo Choi <cw00.choi@samsung.com> - 2016-03-14 09:50 +0100

#1356820 — [PATCH 00/10] ARM: dts: Add new Exynos3250-based ARTIK5 module dtsi file

This patchset add the support for Device Tree source for Samsung ARTIK5 module[1]
based on Exynos3250 SoC and development board[2]. The ARTIK5 module includes
the follwoing devices:
- Application Processor (Samsung Exynos3250)
- WiFi/BT Combo chip
- PMIC (Samsung S2MPS14)
- eMMC (4GB)
- DRAM LPDDR3 (512MB)
- Connectors pin (60 Pins x 3 set)

Also, this patchset add the ARTIK5 development board[2] dts file which includes
the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
ethernet port, uart port and so on.

[1] https://www.artik.io/hardware/artik-5
[2] http://www.digikey.com/product-detail/en/SIP-KITNXB001/1510-1316-ND/5825102

Chanwoo Choi (6):
  clk: samsung: exynos3250: Add MMC2 clock
  ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
  ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module
  ARM: dts: Add thermal zone and cpufreq node for exynos3250-artik5 module
  ARM: dts: Add rtc and adc dt node for exynos3250-artik5 module
  ARM: dts: Add PPMU node for exynos3250-artik5 module

Jaehoon Chung (2):
  ARM: dts: Add MSHC0 dt node for eMMC device for exynos3250-artik5 module
  ARM: dts: Add MSHC2 dt node for SD card for exynos3250-artik5-devel board

Pankaj Dubey (2):
  clk: samsung: exynos3250: Add UART2 clock
  ARM: dts: Add UART2 dt node for Exynos3250 SoC

 arch/arm/boot/dts/Makefile                    |   1 +
 arch/arm/boot/dts/exynos3250-artik5-devel.dts |  42 +++
 arch/arm/boot/dts/exynos3250-artik5.dtsi      | 372 ++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos3250-pinctrl.dtsi     |  42 +++
 arch/arm/boot/dts/exynos3250.dtsi             |  25 ++
 drivers/clk/samsung/clk-exynos3250.c          |  15 ++
 include/dt-bindings/clock/exynos3250.h        |  11 +-
 7 files changed, 507 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/exynos3250-artik5-devel.dts
 create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi

-- 
1.9.1

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#1356822 — [PATCH 01/10] clk: samsung: exynos3250: Add UART2 clock

From: Pankaj Dubey <pankaj.dubey@samsung.com>

This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos3250.c   | 6 ++++++
 include/dt-bindings/clock/exynos3250.h | 6 +++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index fdd41b17a24f..bc60e399d1bc 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
 	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
 
 	/* SRC_PERIL0 */
+	MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
 	MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
 	MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
 
@@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
 	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 
 	/* DIV_PERIL0 */
+	DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
 	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
 	DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
 
@@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
 		GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
 		GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+		GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
 		GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
 	GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
 	GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
 	GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+	GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
 	GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
 	GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
 };
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index 63d01c15d2b3..ddb874130d86 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -79,6 +79,7 @@
 #define CLK_MOUT_CORE			58
 #define CLK_MOUT_APLL			59
 #define CLK_MOUT_ACLK_266_SUB		60
+#define CLK_MOUT_UART2			61
 
 /* Dividers */
 #define CLK_DIV_GPL			64
@@ -127,6 +128,7 @@
 #define CLK_DIV_CORE			107
 #define CLK_DIV_HPM			108
 #define CLK_DIV_COPY			109
+#define CLK_DIV_UART2			110
 
 /* Gates */
 #define CLK_ASYNC_G3D			128
@@ -223,6 +225,7 @@
 #define CLK_BLOCK_MFC			219
 #define CLK_BLOCK_CAM			220
 #define CLK_SMIES			221
+#define CLK_UART2			222
 
 /* Special clocks */
 #define CLK_SCLK_JPEG			224
@@ -249,12 +252,13 @@
 #define CLK_SCLK_SPI0			245
 #define CLK_SCLK_UART1			246
 #define CLK_SCLK_UART0			247
+#define CLK_SCLK_UART2			248
 
 /*
  * Total number of clocks of main CMU.
  * NOTE: Must be equal to last clock ID increased by one.
  */
-#define CLK_NR_CLKS			248
+#define CLK_NR_CLKS			249
 
 /*
  * CMU DMC
-- 
1.9.1

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#1356823 — [PATCH 02/10] clk: samsung: exynos3250: Add MMC2 clock

This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos3250.c   | 9 +++++++++
 include/dt-bindings/clock/exynos3250.h | 7 ++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index bc60e399d1bc..16575ee874cb 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
 
 	/* SRC_FSYS */
 	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+	MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
 	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
 	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
 
@@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = {
 		CLK_SET_RATE_PARENT, 0),
 	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 
+	/* DIV_FSYS2 */
+	DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
 	/* DIV_PERIL0 */
 	DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
 	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
@@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
 		GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
 		GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+		GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
 		GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
@@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
 	GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
 	GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
 	GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+	GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
 	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
 	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
 	GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index ddb874130d86..c796ff02ceeb 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -80,6 +80,7 @@
 #define CLK_MOUT_APLL			59
 #define CLK_MOUT_ACLK_266_SUB		60
 #define CLK_MOUT_UART2			61
+#define CLK_MOUT_MMC2			62
 
 /* Dividers */
 #define CLK_DIV_GPL			64
@@ -129,6 +130,8 @@
 #define CLK_DIV_HPM			108
 #define CLK_DIV_COPY			109
 #define CLK_DIV_UART2			110
+#define CLK_DIV_MMC2_PRE		111
+#define CLK_DIV_MMC2			112
 
 /* Gates */
 #define CLK_ASYNC_G3D			128
@@ -226,6 +229,7 @@
 #define CLK_BLOCK_CAM			220
 #define CLK_SMIES			221
 #define CLK_UART2			222
+#define CLK_SDMMC2			223
 
 /* Special clocks */
 #define CLK_SCLK_JPEG			224
@@ -253,12 +257,13 @@
 #define CLK_SCLK_UART1			246
 #define CLK_SCLK_UART0			247
 #define CLK_SCLK_UART2			248
+#define CLK_SCLK_MMC2			249
 
 /*
  * Total number of clocks of main CMU.
  * NOTE: Must be equal to last clock ID increased by one.
  */
-#define CLK_NR_CLKS			249
+#define CLK_NR_CLKS			250
 
 /*
  * CMU DMC
-- 
1.9.1

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#1356824 — [PATCH 03/10] ARM: dts: Add UART2 dt node for Exynos3250 SoC

From: Pankaj Dubey <pankaj.dubey@samsung.com>

This patch add the uart2 devicetree node for Exynos3250 SoC.

Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 arch/arm/boot/dts/exynos3250-pinctrl.dtsi |  7 +++++++
 arch/arm/boot/dts/exynos3250.dtsi         | 12 ++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index ecf79386e891..54c587f27265 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -158,6 +158,13 @@
 		samsung,pin-drv = <0>;
 	};
 
+	uart2_data: uart2-data {
+		samsung,pins = "gpa1-0", "gpa1-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <0>;
+	};
+
 	i2c3_bus: i2c3-bus {
 		samsung,pins = "gpa1-2", "gpa1-3";
 		samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 18e3deffbf48..076677384d20 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,7 @@
 		i2c7 = &i2c_7;
 		serial0 = &serial_0;
 		serial1 = &serial_1;
+		serial2 = &serial_2;
 	};
 
 	cpus {
@@ -465,6 +466,17 @@
 			status = "disabled";
 		};
 
+		serial_2: serial@13820000 {
+			compatible = "samsung,exynos4210-uart";
+			reg = <0x13820000 0x100>;
+			interrupts = <0 111 0>;
+			clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+			clock-names = "uart", "clk_uart_baud0";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_data>;
+			status = "disabled";
+		};
+
 		i2c_0: i2c@13860000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
1.9.1

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#1356825 — [PATCH 10/10] ARM: dts: Add PPMU node for exynos3250-artik5 module

This patch adds PPMU (Platform Performance Monitoring Unit) Device Tree node
for Exynos3250 based ARTIK5 module. The PPMU node is used to get the
utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos3250-artik5.dtsi | 36 ++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 673883fda480..995356708b7d 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -321,6 +321,42 @@
 	status = "okay";
 };
 
+&ppmu_dmc0 {
+	status = "okay";
+	events {
+		ppmu_dmc0_3: ppmu-event3-dmc0 {
+			event-name = "ppmu-event3-dmc0";
+		};
+	};
+};
+
+&ppmu_dmc1 {
+	status = "okay";
+	events {
+		ppmu_dmc1_3: ppmu-event3-dmc1 {
+			event-name = "ppmu-event3-dmc1";
+		};
+	};
+};
+
+&ppmu_leftbus {
+	status = "okay";
+	events {
+		ppmu_leftbus_3: ppmu-event3-leftbus {
+			event-name = "ppmu-event3-leftbus";
+		};
+	};
+};
+
+&ppmu_rightbus {
+	status = "okay";
+	events {
+		ppmu_rightbus_3: ppmu-event3-rightbus {
+			event-name = "ppmu-event3-rightbus";
+		};
+	};
+};
+
 &tmu {
 	status = "okay";
 };
-- 
1.9.1

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#1357054 — Re: [PATCH 10/10] ARM: dts: Add PPMU node for exynos3250-artik5 module

On 14.03.2016 11:04, Chanwoo Choi wrote:
> This patch adds PPMU (Platform Performance Monitoring Unit) Device Tree node
> for Exynos3250 based ARTIK5 module. The PPMU node is used to get the
> utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos3250-artik5.dtsi | 36 ++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)

What is the status with your devfreq patches? Instead of this one, there
should be just:
	#include "exynos4412-ppmu-common.dtsi"
(squashed into patch 5/10).

Best regards,
Krzysztof

> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> index 673883fda480..995356708b7d 100644
> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> @@ -321,6 +321,42 @@
>  	status = "okay";
>  };
>  
> +&ppmu_dmc0 {
> +	status = "okay";
> +	events {
> +		ppmu_dmc0_3: ppmu-event3-dmc0 {
> +			event-name = "ppmu-event3-dmc0";
> +		};
> +	};
> +};
> +
> +&ppmu_dmc1 {
> +	status = "okay";
> +	events {
> +		ppmu_dmc1_3: ppmu-event3-dmc1 {
> +			event-name = "ppmu-event3-dmc1";
> +		};
> +	};
> +};
> +
> +&ppmu_leftbus {
> +	status = "okay";
> +	events {
> +		ppmu_leftbus_3: ppmu-event3-leftbus {
> +			event-name = "ppmu-event3-leftbus";
> +		};
> +	};
> +};
> +
> +&ppmu_rightbus {
> +	status = "okay";
> +	events {
> +		ppmu_rightbus_3: ppmu-event3-rightbus {
> +			event-name = "ppmu-event3-rightbus";
> +		};
> +	};
> +};
> +
>  &tmu {
>  	status = "okay";
>  };
> 

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#1357060 — Re: [PATCH 10/10] ARM: dts: Add PPMU node for exynos3250-artik5 module

On 2016년 03월 14일 17:34, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> This patch adds PPMU (Platform Performance Monitoring Unit) Device Tree node
>> for Exynos3250 based ARTIK5 module. The PPMU node is used to get the
>> utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos3250-artik5.dtsi | 36 ++++++++++++++++++++++++++++++++
>>  1 file changed, 36 insertions(+)
> 
> What is the status with your devfreq patches? Instead of this one, there
> should be just:
> 	#include "exynos4412-ppmu-common.dtsi"
> (squashed into patch 5/10).

I'm not working the devfreq patches(exynos-bus). Sorry for delay.
I'll again implement them by using DEVFREQ_NOTIFIER style according to (Myungjoo Ham's comment)

I drop the this patch on v2 patchset. After implementing the exynos-bus driver,
I'll send it.

Best Regards,
Chanwoo Choi

> 
> Best regards,
> Krzysztof
> 
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> index 673883fda480..995356708b7d 100644
>> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> @@ -321,6 +321,42 @@
>>  	status = "okay";
>>  };
>>  
>> +&ppmu_dmc0 {
>> +	status = "okay";
>> +	events {
>> +		ppmu_dmc0_3: ppmu-event3-dmc0 {
>> +			event-name = "ppmu-event3-dmc0";
>> +		};
>> +	};
>> +};
>> +
>> +&ppmu_dmc1 {
>> +	status = "okay";
>> +	events {
>> +		ppmu_dmc1_3: ppmu-event3-dmc1 {
>> +			event-name = "ppmu-event3-dmc1";
>> +		};
>> +	};
>> +};
>> +
>> +&ppmu_leftbus {
>> +	status = "okay";
>> +	events {
>> +		ppmu_leftbus_3: ppmu-event3-leftbus {
>> +			event-name = "ppmu-event3-leftbus";
>> +		};
>> +	};
>> +};
>> +
>> +&ppmu_rightbus {
>> +	status = "okay";
>> +	events {
>> +		ppmu_rightbus_3: ppmu-event3-rightbus {
>> +			event-name = "ppmu-event3-rightbus";
>> +		};
>> +	};
>> +};
>> +
>>  &tmu {
>>  	status = "okay";
>>  };
>>
> 
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