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| Started by | Paolo Bonzini <pbonzini@redhat.com> |
|---|---|
| First post | 2016-03-08 12:50 +0100 |
| Last post | 2016-03-10 11:10 +0100 |
| Articles | 3 — 2 participants |
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[PATCH 2/2] KVM: MMU: fix reserved bit check for pte.u=0/pte.w=0/CR0.WP=0/CR4.SMEP=1/EFER.NX=0 Paolo Bonzini <pbonzini@redhat.com> - 2016-03-08 12:50 +0100
Re: [PATCH 2/2] KVM: MMU: fix reserved bit check for pte.u=0/pte.w=0/CR0.WP=0/CR4.SMEP=1/EFER.NX=0 Xiao Guangrong <guangrong.xiao@linux.intel.com> - 2016-03-10 09:40 +0100
Re: [PATCH 2/2] KVM: MMU: fix reserved bit check for pte.u=0/pte.w=0/CR0.WP=0/CR4.SMEP=1/EFER.NX=0 Paolo Bonzini <pbonzini@redhat.com> - 2016-03-10 11:10 +0100
| From | Paolo Bonzini <pbonzini@redhat.com> |
|---|---|
| Date | 2016-03-08 12:50 +0100 |
| Subject | [PATCH 2/2] KVM: MMU: fix reserved bit check for pte.u=0/pte.w=0/CR0.WP=0/CR4.SMEP=1/EFER.NX=0 |
| Message-ID | <raojg-hv-3@gated-at.bofh.it> |
KVM handles supervisor writes of a pte.u=0/pte.w=0/CR0.WP=0 page by
setting U=0 and W=1 in the shadow PTE. This will cause a user write
to fault and a supervisor write to succeed (which is correct because
CR0.WP=0). A user read instead will flip U=0 to 1 and W=1 back to 0.
This enables user reads; it also disables supervisor writes, the next
of which will then flip the bits again.
When SMEP is in effect, however, pte.u=0 will enable kernel execution
of this page. To avoid this, KVM also sets pte.nx=1. The reserved bit
catches this because it only looks at the guest's EFER.NX bit. Teach it
that smep_andnot_wp will also use the NX bit of SPTEs.
Cc: stable@vger.kernel.org
Cc: Xiao Guangrong <guangrong.xiao@redhat.com>
Fixes: c258b62b264fdc469b6d3610a907708068145e3b
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
arch/x86/kvm/mmu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 95a955de5964..0cd4ee01de94 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -3721,13 +3721,15 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
void
reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
{
+ int uses_nx = context->nx || context->base_role.smep_andnot_wp;
+
/*
* Passing "true" to the last argument is okay; it adds a check
* on bit 8 of the SPTEs which KVM doesn't use anyway.
*/
__reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
boot_cpu_data.x86_phys_bits,
- context->shadow_root_level, context->nx,
+ context->shadow_root_level, uses_nx,
guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
true);
}
--
1.8.3.1
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| From | Xiao Guangrong <guangrong.xiao@linux.intel.com> |
|---|---|
| Date | 2016-03-10 09:40 +0100 |
| Subject | Re: [PATCH 2/2] KVM: MMU: fix reserved bit check for pte.u=0/pte.w=0/CR0.WP=0/CR4.SMEP=1/EFER.NX=0 |
| Message-ID | <rb4iu-4fF-17@gated-at.bofh.it> |
| In reply to | #1352924 |
On 03/08/2016 07:44 PM, Paolo Bonzini wrote:
> KVM handles supervisor writes of a pte.u=0/pte.w=0/CR0.WP=0 page by
> setting U=0 and W=1 in the shadow PTE. This will cause a user write
> to fault and a supervisor write to succeed (which is correct because
> CR0.WP=0). A user read instead will flip U=0 to 1 and W=1 back to 0.
> This enables user reads; it also disables supervisor writes, the next
> of which will then flip the bits again.
>
> When SMEP is in effect, however, pte.u=0 will enable kernel execution
> of this page. To avoid this, KVM also sets pte.nx=1. The reserved bit
> catches this because it only looks at the guest's EFER.NX bit. Teach it
> that smep_andnot_wp will also use the NX bit of SPTEs.
>
> Cc: stable@vger.kernel.org
> Cc: Xiao Guangrong <guangrong.xiao@redhat.com>
As a redhat guy i am so proud. :)
> Fixes: c258b62b264fdc469b6d3610a907708068145e3b
Thanks for you fixing it, Paolo!
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> arch/x86/kvm/mmu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
> index 95a955de5964..0cd4ee01de94 100644
> --- a/arch/x86/kvm/mmu.c
> +++ b/arch/x86/kvm/mmu.c
> @@ -3721,13 +3721,15 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
> void
> reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
> {
> + int uses_nx = context->nx || context->base_role.smep_andnot_wp;
It would be better if it is 'bool'
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| From | Paolo Bonzini <pbonzini@redhat.com> |
|---|---|
| Date | 2016-03-10 11:10 +0100 |
| Subject | Re: [PATCH 2/2] KVM: MMU: fix reserved bit check for pte.u=0/pte.w=0/CR0.WP=0/CR4.SMEP=1/EFER.NX=0 |
| Message-ID | <rb5Hz-5r7-13@gated-at.bofh.it> |
| In reply to | #1354924 |
On 10/03/2016 09:36, Xiao Guangrong wrote:
>
>
> On 03/08/2016 07:44 PM, Paolo Bonzini wrote:
>> KVM handles supervisor writes of a pte.u=0/pte.w=0/CR0.WP=0 page by
>> setting U=0 and W=1 in the shadow PTE. This will cause a user write
>> to fault and a supervisor write to succeed (which is correct because
>> CR0.WP=0). A user read instead will flip U=0 to 1 and W=1 back to 0.
>> This enables user reads; it also disables supervisor writes, the next
>> of which will then flip the bits again.
>>
>> When SMEP is in effect, however, pte.u=0 will enable kernel execution
>> of this page. To avoid this, KVM also sets pte.nx=1. The reserved bit
>> catches this because it only looks at the guest's EFER.NX bit. Teach it
>> that smep_andnot_wp will also use the NX bit of SPTEs.
>>
>> Cc: stable@vger.kernel.org
>> Cc: Xiao Guangrong <guangrong.xiao@redhat.com>
>
> As a redhat guy i am so proud. :)
>
>> Fixes: c258b62b264fdc469b6d3610a907708068145e3b
>
> Thanks for you fixing it, Paolo!
>
> Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>> ---
>> arch/x86/kvm/mmu.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
>> index 95a955de5964..0cd4ee01de94 100644
>> --- a/arch/x86/kvm/mmu.c
>> +++ b/arch/x86/kvm/mmu.c
>> @@ -3721,13 +3721,15 @@ static void reset_rsvds_bits_mask_ept(struct
>> kvm_vcpu *vcpu,
>> void
>> reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu
>> *context)
>> {
>> + int uses_nx = context->nx || context->base_role.smep_andnot_wp;
>
> It would be better if it is 'bool'
Ok, will do.
Paolo
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