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RE: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR

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  RE: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui <yunhui.cui@nxp.com> - 2016-07-21 18:30 +0200
    Re: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Brian Norris <computersforpeace@gmail.com> - 2016-07-21 19:20 +0200
      Re: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Han Xu <xhnjupt@gmail.com> - 2016-07-21 21:40 +0200

#1447996 — RE: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR

Hi David,

Could you please help to review this patch set.
This patch set is very importmant for fsl-quadspi driver. 

Thanks.


Thursday, June 30, 2016 9:54 AM Yunhui Cui wrote:
> Hi Brian and Han,
> Could you please give me some comments about this patch set v2 ?
> 
> Thanks
> 
> > -----Original Message-----
> > From: Yunhui Cui [mailto:B56489@freescale.com]
> > Sent: Friday, April 22, 2016 2:40 PM
> > To: dwmw2@infradead.org; computersforpeace@gmail.com;
> > han.xu@freescale.com
> > Cc: linux-kernel@vger.kernel.org; linux-mtd@lists.infradead.org;
> > linux- arm-kernel@lists.infradead.org; Yao Yuan; Yunhui Cui
> > Subject: [PATCH v2 1/9] mtd:fsl-quadspi:use the property fields of
> > SPI- NOR
> >
> > We can get the read/write/erase opcode from the spi nor framework
> > directly. This patch uses the information stored in the SPI-NOR to
> > remove the hardcode in the fsl_qspi_init_lut().
> >
> > Signed-off-by: Yunhui Cui <B56489@freescale.com>
> > Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> > ---
> >  drivers/mtd/spi-nor/fsl-quadspi.c | 40
> > ++++++++++++---------------------
> > ------
> >  1 file changed, 12 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c
> > b/drivers/mtd/spi-nor/fsl- quadspi.c index 9ab2b51..517ffe2 100644
> > --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> > @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> >  	void __iomem *base = q->iobase;
> >  	int rxfifo = q->devtype_data->rxfifo;
> >  	u32 lut_base;
> > -	u8 cmd, addrlen, dummy;
> >  	int i;
> >
> > +	struct spi_nor *nor = &q->nor[0];
> > +	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
> > +	u8 read_op = nor->read_opcode;
> > +	u8 read_dm = nor->read_dummy;
> > +
> >  	fsl_qspi_unlock_lut(q);
> >
> >  	/* Clear all the LUT table */
> > @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> >  	/* Quad Read */
> >  	lut_base = SEQID_QUAD_READ * 4;
> >
> > -	if (q->nor_size <= SZ_16M) {
> > -		cmd = SPINOR_OP_READ_1_1_4;
> > -		addrlen = ADDR24BIT;
> > -		dummy = 8;
> > -	} else {
> > -		/* use the 4-byte address */
> > -		cmd = SPINOR_OP_READ_1_1_4;
> > -		addrlen = ADDR32BIT;
> > -		dummy = 8;
> > -	}
> > -
> > -	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> > +	qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
> >  			base + QUADSPI_LUT(lut_base));
> > -	qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4,
> > rxfifo),
> > +	qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
> > +		    LUT1(FSL_READ, PAD4, rxfifo),
> >  			base + QUADSPI_LUT(lut_base + 1));
> >
> >  	/* Write enable */
> > @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
> >  	/* Page Program */
> >  	lut_base = SEQID_PP * 4;
> >
> > -	if (q->nor_size <= SZ_16M) {
> > -		cmd = SPINOR_OP_PP;
> > -		addrlen = ADDR24BIT;
> > -	} else {
> > -		/* use the 4-byte address */
> > -		cmd = SPINOR_OP_PP;
> > -		addrlen = ADDR32BIT;
> > -	}
> > -
> > -	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> > +	qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
> > +		    LUT1(ADDR, PAD1, addrlen),
> >  			base + QUADSPI_LUT(lut_base));
> >  	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
> >  			base + QUADSPI_LUT(lut_base + 1)); @@ -432,10 +418,8 @@
> static
> > void fsl_qspi_init_lut(struct fsl_qspi *q)
> >  	/* Erase a sector */
> >  	lut_base = SEQID_SE * 4;
> >
> > -	cmd = q->nor[0].erase_opcode;
> > -	addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
> > -
> > -	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> > +	qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
> > +		    LUT1(ADDR, PAD1, addrlen),
> >  			base + QUADSPI_LUT(lut_base));
> >
> >  	/* Erase the whole chip */
> > --
> > 2.1.0.27.g96db324

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#1448020

On Thu, Jul 21, 2016 at 05:58:48AM +0000, Yunhui Cui wrote:
> Could you please help to review this patch set.
> This patch set is very importmant for fsl-quadspi driver. 

I didn't want this to be my only comment, but since you're pinging
again...

Your patchset doesn't build on the latest. You need to refresh.

Also, has Han Xu reviewed this?

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#1448098

On Thu, Jul 21, 2016 at 12:09 PM, Brian Norris
<computersforpeace@gmail.com> wrote:
> On Thu, Jul 21, 2016 at 05:58:48AM +0000, Yunhui Cui wrote:
>> Could you please help to review this patch set.
>> This patch set is very importmant for fsl-quadspi driver.
>
> I didn't want this to be my only comment, but since you're pinging
> again...
>
> Your patchset doesn't build on the latest. You need to refresh.
>
> Also, has Han Xu reviewed this?

I sent comments for v1 in [PATCH 6/9] mtd: spi-nor: Support R/W for
S25FS-S family flash,
but nothing changed in v2. Brian, could you please check my comment
which related to spi-nor
driver.

>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/



-- 
Sincerely,

Han XU

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