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Groups > linux.kernel > #1447754 > unrolled thread
| Started by | Joao Pinto <Joao.Pinto@synopsys.com> |
|---|---|
| First post | 2016-07-21 11:50 +0200 |
| Last post | 2016-07-21 12:00 +0200 |
| Articles | 2 — 1 participant |
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[PATCH 0/2] pcie-designware: add iATU unroll feature Joao Pinto <Joao.Pinto@synopsys.com> - 2016-07-21 11:50 +0200
[PATCH 2/2] pcie-designware: add core version Joao Pinto <Joao.Pinto@synopsys.com> - 2016-07-21 12:00 +0200
| From | Joao Pinto <Joao.Pinto@synopsys.com> |
|---|---|
| Date | 2016-07-21 11:50 +0200 |
| Subject | [PATCH 0/2] pcie-designware: add iATU unroll feature |
| Message-ID | <rXiMa-5GH-19@gated-at.bofh.it> |
The new DWC PCIe Core version (4.80) implements iATU in a different way. This new mechanism is called iATU Unroll Mode. The Core still supports the "old" mechanism calling it Legacy Mode if configured to do so, but the standard way will be using Unroll. This patch adds the necessary support for the mechanism and makes some minor improvements to the existent one. Joao Pinto (2): pcie-designware: adding iATU Unroll feature pcie-designware: add core version drivers/pci/host/pcie-designware.c | 164 +++++++++++++++++++++++++++++++++---- drivers/pci/host/pcie-designware.h | 6 +- 2 files changed, 151 insertions(+), 19 deletions(-) -- 1.8.1.5
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| From | Joao Pinto <Joao.Pinto@synopsys.com> |
|---|---|
| Date | 2016-07-21 12:00 +0200 |
| Subject | [PATCH 2/2] pcie-designware: add core version |
| Message-ID | <rXiVQ-5LD-31@gated-at.bofh.it> |
| In reply to | #1447754 |
The Core version information is available since version 4.70. This patch adds to the driver the register and default value for new core 4.80 if needed in some future work. Signed-off-by: Joao Pinto <jpinto@synopsys.com> --- drivers/pci/host/pcie-designware.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index c673e6c..1f40288 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -34,6 +34,10 @@ #define LINK_WAIT_IATU_MIN 9000 #define LINK_WAIT_IATU_MAX 10000 +/* Core version (available from core 4.70) */ +#define PCIE_CORE_VERSION 0x8F8 +#define PCIE_CORE_VERSION_480A 0x3438302a + /* Synopsys specific PCIE configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_MODE_MASK (0x3f << 16) -- 1.8.1.5
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