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[PATCH 1/1] EDAC, sb_edac: Fix channel reporting on Knights Landing

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  [PATCH 1/1] EDAC, sb_edac: Fix channel reporting on Knights Landing Lukasz Odzioba <lukasz.odzioba@intel.com> - 2016-07-23 01:50 +0200

#1448838 — [PATCH 1/1] EDAC, sb_edac: Fix channel reporting on Knights Landing

On Intel Xeon Phi Knights Landing processor family the channels
of memory controller have untypical arrangement - MC0 is mapped to
CH3,4,5 and MC1 is mapped to CH0,1,2. This causes EDAC driver to
report the channel name incorrectly.

We missed this change earlier, so the code already contains
similar comment, but the translation function is incorrect.

Without this patch:
  errors in DIMM_A and DIMM_D were reported in DIMM_D
  errors in DIMM_B and DIMM_E were reported in DIMM_E
  errors in DIMM_C and DIMM_F were reported in DIMM_F

Fixes: d0cdf9003140 ("sb_edac: Add Knights Landing (Xeon Phi gen 2) support")
Signed-off-by: Lukasz Odzioba <lukasz.odzioba@intel.com>
Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
---
 drivers/edac/sb_edac.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 6744d88..61e2c52 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -552,9 +552,9 @@ static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 /* Knight's Landing Support */
 /*
  * KNL's memory channels are swizzled between memory controllers.
- * MC0 is mapped to CH3,5,6 and MC1 is mapped to CH0,1,2
+ * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2
  */
-#define knl_channel_remap(channel) ((channel + 3) % 6)
+#define knl_channel_remap(mc, chan) (mc ? chan : chan + 3)
 
 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC       0x7840
@@ -1286,7 +1286,7 @@ static u32 knl_get_mc_route(int entry, u32 reg)
 	mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
 	chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
 
-	return knl_channel_remap(mc*3 + chan);
+	return knl_channel_remap(mc, chan);
 }
 
 /*
@@ -3003,9 +3003,16 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
 				mscod, errcode,
 				m->bank);
 		} else {
-			char A = *("A");
+			char mc, A = *("A");
 
-			channel = knl_channel_remap(channel);
+			/*
+			 * Reported channel is in range 0-2, so we can't map it
+			 * back to mc. To figure out mc we check machine check
+			 * bank register that reported this error.
+			 * bank15 means mc0 and bank16 means mc1.
+			 */
+			mc = m->bank == 16;
+			channel = knl_channel_remap(mc, channel);
 			channel_mask = 1 << channel;
 			snprintf(msg, sizeof(msg),
 				"%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
-- 
1.8.3.1

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