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| Started by | Lin Huang <hl@rock-chips.com> |
|---|---|
| First post | 2016-07-22 11:10 +0200 |
| Last post | 2016-07-22 12:10 +0200 |
| Articles | 2 — 2 participants |
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[PATCH v3 3/7] clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc Lin Huang <hl@rock-chips.com> - 2016-07-22 11:10 +0200
Re: [PATCH v3 3/7] clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc Heiko Stübner <heiko@sntech.de> - 2016-07-22 12:10 +0200
| From | Lin Huang <hl@rock-chips.com> |
|---|---|
| Date | 2016-07-22 11:10 +0200 |
| Subject | [PATCH v3 3/7] clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc |
| Message-ID | <rXED0-3Mr-5@gated-at.bofh.it> |
Signed-off-by: Lin Huang <hl@rock-chips.com> --- Changes in v3: -None Changes in v2: - None Changes in v1: - None include/dt-bindings/clock/rk3399-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..8a0f0442 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,7 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_DDRCLK 168 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 2.6.6
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| From | Heiko Stübner <heiko@sntech.de> |
|---|---|
| Date | 2016-07-22 12:10 +0200 |
| Message-ID | <rXFz4-4pM-3@gated-at.bofh.it> |
| In reply to | #1448479 |
Am Freitag, 22. Juli 2016, 17:07:16 schrieb Lin Huang: > Signed-off-by: Lin Huang <hl@rock-chips.com> > --- > Changes in v3: > -None > > Changes in v2: > - None > Changes in v1: > - None > > include/dt-bindings/clock/rk3399-cru.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/dt-bindings/clock/rk3399-cru.h > b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..8a0f0442 100644 > --- a/include/dt-bindings/clock/rk3399-cru.h > +++ b/include/dt-bindings/clock/rk3399-cru.h > @@ -131,6 +131,7 @@ > #define SCLK_DPHY_RX0_CFG 165 > #define SCLK_RMII_SRC 166 > #define SCLK_PCIEPHY_REF100M 167 > +#define SCLK_DDRCLK 168 nit: SCLK_DDR (i.e. without the CLK at the end)? > #define DCLK_VOP0 180 > #define DCLK_VOP1 181
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