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| Started by | Adrian Hunter <adrian.hunter@intel.com> |
|---|---|
| First post | 2016-07-19 15:00 +0200 |
| Last post | 2016-07-20 10:40 +0200 |
| Articles | 6 — 2 participants |
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[PATCH 0/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter <adrian.hunter@intel.com> - 2016-07-19 15:00 +0200
[PATCH 1/2] x86/insn: perf tools: Fix vcvtph2ps instruction decoding Adrian Hunter <adrian.hunter@intel.com> - 2016-07-19 15:00 +0200
Re: [PATCH 1/2] x86/insn: perf tools: Fix vcvtph2ps instruction decoding Masami Hiramatsu <mhiramat@kernel.org> - 2016-07-20 02:40 +0200
Re: [PATCH 0/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Masami Hiramatsu <mhiramat@kernel.org> - 2016-07-20 02:30 +0200
Re: [PATCH 2/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Masami Hiramatsu <mhiramat@kernel.org> - 2016-07-20 04:00 +0200
Re: [PATCH 2/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder Adrian Hunter <adrian.hunter@intel.com> - 2016-07-20 10:40 +0200
| From | Adrian Hunter <adrian.hunter@intel.com> |
|---|---|
| Date | 2016-07-19 15:00 +0200 |
| Subject | [PATCH 0/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder |
| Message-ID | <rWCN0-47Q-15@gated-at.bofh.it> |
Hi
Here is a patch to add support for Intel's AVX-512 instructions to the
instruction decoder. Also there is a patch to fix vcvtph2ps.
AVX-512 instructions are documented in Intel Architecture Instruction Set
Extensions Programming Reference (February 2016).
These patches do not conflict with Dan's removal of pcommit.
Adrian Hunter (2):
x86/insn: perf tools: Fix vcvtph2ps instruction decoding
x86/insn: perf tools: Add AVX-512 support to the instruction decoder
arch/x86/include/asm/inat.h | 17 +-
arch/x86/include/asm/insn.h | 12 +-
arch/x86/lib/insn.c | 18 +-
arch/x86/lib/x86-opcode-map.txt | 263 ++-
arch/x86/tools/gen-insn-attr-x86.awk | 11 +-
tools/perf/arch/x86/tests/insn-x86-dat-32.c | 1018 ++++++++++-
tools/perf/arch/x86/tests/insn-x86-dat-64.c | 940 +++++++++-
tools/perf/arch/x86/tests/insn-x86-dat-src.c | 1789 ++++++++++++++++++++
.../util/intel-pt-decoder/gen-insn-attr-x86.awk | 11 +-
tools/perf/util/intel-pt-decoder/inat.h | 17 +-
tools/perf/util/intel-pt-decoder/insn.c | 18 +-
tools/perf/util/intel-pt-decoder/insn.h | 12 +-
.../perf/util/intel-pt-decoder/x86-opcode-map.txt | 263 ++-
13 files changed, 4179 insertions(+), 210 deletions(-)
Regards
Adrian
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| From | Adrian Hunter <adrian.hunter@intel.com> |
|---|---|
| Date | 2016-07-19 15:00 +0200 |
| Subject | [PATCH 1/2] x86/insn: perf tools: Fix vcvtph2ps instruction decoding |
| Message-ID | <rWCN1-47Q-27@gated-at.bofh.it> |
| In reply to | #1446417 |
vcvtph2ps does not have an immediate operand, so remove the erroneous 'Ib'
from its opcode map entry. Add vcvtph2ps to the perf tools new
instructions test to verify it.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
arch/x86/lib/x86-opcode-map.txt | 2 +-
tools/perf/arch/x86/tests/insn-x86-dat-32.c | 10 ++++++----
tools/perf/arch/x86/tests/insn-x86-dat-64.c | 10 ++++++----
tools/perf/arch/x86/tests/insn-x86-dat-src.c | 4 ++++
tools/perf/util/intel-pt-decoder/x86-opcode-map.txt | 2 +-
5 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index d388de72eaca..28082de46f0d 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -629,7 +629,7 @@ AVXcode: 2
10: pblendvb Vdq,Wdq (66)
11:
12:
-13: vcvtph2ps Vx,Wx,Ib (66),(v)
+13: vcvtph2ps Vx,Wx (66),(v)
14: blendvps Vdq,Wdq (66)
15: blendvpd Vdq,Wdq (66)
16: vpermps Vqq,Hqq,Wqq (66),(v)
diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c
index 3b491cfe204e..ca08e6eb988f 100644
--- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c
+++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c
@@ -6,6 +6,8 @@
{{0x0f, 0x31, }, 2, 0, "", "",
"0f 31 \trdtsc ",},
+{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
+"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
"f3 0f 1b 00 \tbndmk (%eax),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
@@ -309,19 +311,19 @@
{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",},
{{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional",
-"f2 e8 fc ff ff ff \tbnd call 3c3 <main+0x3c3>",},
+"f2 e8 fc ff ff ff \tbnd call 3c8 <main+0x3c8>",},
{{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect",
"f2 ff 10 \tbnd call *(%eax)",},
{{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
"f2 c3 \tbnd ret ",},
{{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional",
-"f2 e9 fc ff ff ff \tbnd jmp 3ce <main+0x3ce>",},
+"f2 e9 fc ff ff ff \tbnd jmp 3d3 <main+0x3d3>",},
{{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional",
-"f2 e9 fc ff ff ff \tbnd jmp 3d4 <main+0x3d4>",},
+"f2 e9 fc ff ff ff \tbnd jmp 3d9 <main+0x3d9>",},
{{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect",
"f2 ff 21 \tbnd jmp *(%ecx)",},
{{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional",
-"f2 0f 85 fc ff ff ff \tbnd jne 3de <main+0x3de>",},
+"f2 0f 85 fc ff ff ff \tbnd jne 3e3 <main+0x3e3>",},
{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
"0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",},
{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c
index 4fe7cce179c4..262d9d25a6fa 100644
--- a/tools/perf/arch/x86/tests/insn-x86-dat-64.c
+++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c
@@ -6,6 +6,8 @@
{{0x0f, 0x31, }, 2, 0, "", "",
"0f 31 \trdtsc ",},
+{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
+"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
"f3 0f 1b 00 \tbndmk (%rax),%bnd0",},
{{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
@@ -325,19 +327,19 @@
{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",},
{{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional",
-"f2 e8 00 00 00 00 \tbnd callq 3f6 <main+0x3f6>",},
+"f2 e8 00 00 00 00 \tbnd callq 3fb <main+0x3fb>",},
{{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",
"67 f2 ff 10 \tbnd callq *(%eax)",},
{{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
"f2 c3 \tbnd retq ",},
{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
-"f2 e9 00 00 00 00 \tbnd jmpq 402 <main+0x402>",},
+"f2 e9 00 00 00 00 \tbnd jmpq 407 <main+0x407>",},
{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
-"f2 e9 00 00 00 00 \tbnd jmpq 408 <main+0x408>",},
+"f2 e9 00 00 00 00 \tbnd jmpq 40d <main+0x40d>",},
{{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect",
"67 f2 ff 21 \tbnd jmpq *(%ecx)",},
{{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional",
-"f2 0f 85 00 00 00 00 \tbnd jne 413 <main+0x413>",},
+"f2 0f 85 00 00 00 00 \tbnd jne 418 <main+0x418>",},
{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
"0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",},
{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c
index 41b1b1c62660..3cd677513e9e 100644
--- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c
+++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c
@@ -19,6 +19,10 @@ int main(void)
/* Following line is a marker for the awk script - do not change */
asm volatile("rdtsc"); /* Start here */
+ /* Test fix for vcvtph2ps in x86-opcode-map.txt */
+
+ asm volatile("vcvtph2ps %xmm3,%ymm5");
+
#ifdef __x86_64__
/* bndmk m64, bnd */
diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
index d388de72eaca..28082de46f0d 100644
--- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
+++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
@@ -629,7 +629,7 @@ AVXcode: 2
10: pblendvb Vdq,Wdq (66)
11:
12:
-13: vcvtph2ps Vx,Wx,Ib (66),(v)
+13: vcvtph2ps Vx,Wx (66),(v)
14: blendvps Vdq,Wdq (66)
15: blendvpd Vdq,Wdq (66)
16: vpermps Vqq,Hqq,Wqq (66),(v)
--
1.9.1
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| From | Masami Hiramatsu <mhiramat@kernel.org> |
|---|---|
| Date | 2016-07-20 02:40 +0200 |
| Subject | Re: [PATCH 1/2] x86/insn: perf tools: Fix vcvtph2ps instruction decoding |
| Message-ID | <rWNIl-2BH-13@gated-at.bofh.it> |
| In reply to | #1446422 |
On Tue, 19 Jul 2016 15:46:47 +0300
Adrian Hunter <adrian.hunter@intel.com> wrote:
> vcvtph2ps does not have an immediate operand, so remove the erroneous 'Ib'
> from its opcode map entry. Add vcvtph2ps to the perf tools new
> instructions test to verify it.
Hmm, Intel SDM Vol.2D Table A-4 shows vcvtph2ps has Ib (Vol.2C Figure 5-6.
also has same mistake in title), but yes, instruction set reference of VCVTPH2PS
shows that has no immediate. So, I guess OPCODE MAP should be fixed.
Looks good to me:)
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Thank you!
>
> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> arch/x86/lib/x86-opcode-map.txt | 2 +-
> tools/perf/arch/x86/tests/insn-x86-dat-32.c | 10 ++++++----
> tools/perf/arch/x86/tests/insn-x86-dat-64.c | 10 ++++++----
> tools/perf/arch/x86/tests/insn-x86-dat-src.c | 4 ++++
> tools/perf/util/intel-pt-decoder/x86-opcode-map.txt | 2 +-
> 5 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
> index d388de72eaca..28082de46f0d 100644
> --- a/arch/x86/lib/x86-opcode-map.txt
> +++ b/arch/x86/lib/x86-opcode-map.txt
> @@ -629,7 +629,7 @@ AVXcode: 2
> 10: pblendvb Vdq,Wdq (66)
> 11:
> 12:
> -13: vcvtph2ps Vx,Wx,Ib (66),(v)
> +13: vcvtph2ps Vx,Wx (66),(v)
> 14: blendvps Vdq,Wdq (66)
> 15: blendvpd Vdq,Wdq (66)
> 16: vpermps Vqq,Hqq,Wqq (66),(v)
> diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c
> index 3b491cfe204e..ca08e6eb988f 100644
> --- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c
> +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c
> @@ -6,6 +6,8 @@
>
> {{0x0f, 0x31, }, 2, 0, "", "",
> "0f 31 \trdtsc ",},
> +{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
> +"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
> {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
> "f3 0f 1b 00 \tbndmk (%eax),%bnd0",},
> {{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
> @@ -309,19 +311,19 @@
> {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
> "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",},
> {{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional",
> -"f2 e8 fc ff ff ff \tbnd call 3c3 <main+0x3c3>",},
> +"f2 e8 fc ff ff ff \tbnd call 3c8 <main+0x3c8>",},
> {{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect",
> "f2 ff 10 \tbnd call *(%eax)",},
> {{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
> "f2 c3 \tbnd ret ",},
> {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional",
> -"f2 e9 fc ff ff ff \tbnd jmp 3ce <main+0x3ce>",},
> +"f2 e9 fc ff ff ff \tbnd jmp 3d3 <main+0x3d3>",},
> {{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional",
> -"f2 e9 fc ff ff ff \tbnd jmp 3d4 <main+0x3d4>",},
> +"f2 e9 fc ff ff ff \tbnd jmp 3d9 <main+0x3d9>",},
> {{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect",
> "f2 ff 21 \tbnd jmp *(%ecx)",},
> {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional",
> -"f2 0f 85 fc ff ff ff \tbnd jne 3de <main+0x3de>",},
> +"f2 0f 85 fc ff ff ff \tbnd jne 3e3 <main+0x3e3>",},
> {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
> "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",},
> {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
> diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c
> index 4fe7cce179c4..262d9d25a6fa 100644
> --- a/tools/perf/arch/x86/tests/insn-x86-dat-64.c
> +++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c
> @@ -6,6 +6,8 @@
>
> {{0x0f, 0x31, }, 2, 0, "", "",
> "0f 31 \trdtsc ",},
> +{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
> +"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
> {{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
> "f3 0f 1b 00 \tbndmk (%rax),%bnd0",},
> {{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
> @@ -325,19 +327,19 @@
> {{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
> "0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",},
> {{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional",
> -"f2 e8 00 00 00 00 \tbnd callq 3f6 <main+0x3f6>",},
> +"f2 e8 00 00 00 00 \tbnd callq 3fb <main+0x3fb>",},
> {{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",
> "67 f2 ff 10 \tbnd callq *(%eax)",},
> {{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
> "f2 c3 \tbnd retq ",},
> {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
> -"f2 e9 00 00 00 00 \tbnd jmpq 402 <main+0x402>",},
> +"f2 e9 00 00 00 00 \tbnd jmpq 407 <main+0x407>",},
> {{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
> -"f2 e9 00 00 00 00 \tbnd jmpq 408 <main+0x408>",},
> +"f2 e9 00 00 00 00 \tbnd jmpq 40d <main+0x40d>",},
> {{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect",
> "67 f2 ff 21 \tbnd jmpq *(%ecx)",},
> {{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional",
> -"f2 0f 85 00 00 00 00 \tbnd jne 413 <main+0x413>",},
> +"f2 0f 85 00 00 00 00 \tbnd jne 418 <main+0x418>",},
> {{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
> "0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",},
> {{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
> diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c
> index 41b1b1c62660..3cd677513e9e 100644
> --- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c
> +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c
> @@ -19,6 +19,10 @@ int main(void)
> /* Following line is a marker for the awk script - do not change */
> asm volatile("rdtsc"); /* Start here */
>
> + /* Test fix for vcvtph2ps in x86-opcode-map.txt */
> +
> + asm volatile("vcvtph2ps %xmm3,%ymm5");
> +
> #ifdef __x86_64__
>
> /* bndmk m64, bnd */
> diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
> index d388de72eaca..28082de46f0d 100644
> --- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
> +++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
> @@ -629,7 +629,7 @@ AVXcode: 2
> 10: pblendvb Vdq,Wdq (66)
> 11:
> 12:
> -13: vcvtph2ps Vx,Wx,Ib (66),(v)
> +13: vcvtph2ps Vx,Wx (66),(v)
> 14: blendvps Vdq,Wdq (66)
> 15: blendvpd Vdq,Wdq (66)
> 16: vpermps Vqq,Hqq,Wqq (66),(v)
> --
> 1.9.1
>
--
Masami Hiramatsu <mhiramat@kernel.org>
[toc] | [prev] | [next] | [standalone]
| From | Masami Hiramatsu <mhiramat@kernel.org> |
|---|---|
| Date | 2016-07-20 02:30 +0200 |
| Subject | Re: [PATCH 0/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder |
| Message-ID | <rWNyF-2yx-9@gated-at.bofh.it> |
| In reply to | #1446417 |
On Tue, 19 Jul 2016 15:46:46 +0300 Adrian Hunter <adrian.hunter@intel.com> wrote: > Hi > > Here is a patch to add support for Intel's AVX-512 instructions to the > instruction decoder. Also there is a patch to fix vcvtph2ps. > > AVX-512 instructions are documented in Intel Architecture Instruction Set > Extensions Programming Reference (February 2016). Great job! I'll check it. Thank you! > > These patches do not conflict with Dan's removal of pcommit. > > > Adrian Hunter (2): > x86/insn: perf tools: Fix vcvtph2ps instruction decoding > x86/insn: perf tools: Add AVX-512 support to the instruction decoder > > arch/x86/include/asm/inat.h | 17 +- > arch/x86/include/asm/insn.h | 12 +- > arch/x86/lib/insn.c | 18 +- > arch/x86/lib/x86-opcode-map.txt | 263 ++- > arch/x86/tools/gen-insn-attr-x86.awk | 11 +- > tools/perf/arch/x86/tests/insn-x86-dat-32.c | 1018 ++++++++++- > tools/perf/arch/x86/tests/insn-x86-dat-64.c | 940 +++++++++- > tools/perf/arch/x86/tests/insn-x86-dat-src.c | 1789 ++++++++++++++++++++ > .../util/intel-pt-decoder/gen-insn-attr-x86.awk | 11 +- > tools/perf/util/intel-pt-decoder/inat.h | 17 +- > tools/perf/util/intel-pt-decoder/insn.c | 18 +- > tools/perf/util/intel-pt-decoder/insn.h | 12 +- > .../perf/util/intel-pt-decoder/x86-opcode-map.txt | 263 ++- > 13 files changed, 4179 insertions(+), 210 deletions(-) > > > Regards > Adrian -- Masami Hiramatsu <mhiramat@kernel.org>
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| From | Masami Hiramatsu <mhiramat@kernel.org> |
|---|---|
| Date | 2016-07-20 04:00 +0200 |
| Subject | Re: [PATCH 2/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder |
| Message-ID | <rWOXM-3jD-9@gated-at.bofh.it> |
| In reply to | #1446417 |
On Tue, 19 Jul 2016 15:46:48 +0300 Adrian Hunter <adrian.hunter@intel.com> wrote: > Add support for Intel's AVX-512 instructions to the instruction decoder. > > AVX-512 instructions are documented in Intel Architecture Instruction Set > Extensions Programming Reference (February 2016). > > AVX-512 instructions are identifed by a EVEX prefix which, for the purpose > of instruction decoding, can be treated as though it were a 4-byte VEX > prefix. > > Existing instructions which can now accept an EVEX prefix need not be > further annotated in the op code map (x86-opcode-map.txt). In the case of > new instructions, the op code map is updated accordingly. > > Also add associated Mask Instructions that are used to manipulate mask > registers used in AVX-512 instructions. > > Add a representative set of instructions to the perf tools new instructons > test. Hmm, could you split this patch into 2 or 3 parts for review? One is for core-kernel, the others are for perf tools (feature adding and tests). [..] > diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt > index 28082de46f0d..92b89fa5f414 100644 > --- a/arch/x86/lib/x86-opcode-map.txt > +++ b/arch/x86/lib/x86-opcode-map.txt > @@ -13,12 +13,17 @@ > # opcode: escape # escaped-name > # EndTable > # > +# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix > +# mnemonics that begin with lowercase 'k' accept a VEX prefix > +# Ah, nice :) > #<group maps> > # GrpTable: GrpXXX > # reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...] > # EndTable > # > # AVX Superscripts > +# (ev): this opcode requires EVEX prefix. > +# (evo): this opcode accepts EVEX prefix. Hmm, what the 'o' stands for? I thought it means "EVEX ONLY", but the comment is opposite. For example, see 'o64', which means "64bit only". And anyway, as you said above, if all existing instructions can accept EVEX prefix, why would we need it? > -5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) > +5b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) Ah, I see, so that is for the instructions which change the mnemonic since byte-width is changed... OK, so please update the above description of the superscript, like as "this opcode is changed by EVEX prefix (EVEX opcode)" etc. Thank you, -- Masami Hiramatsu <mhiramat@kernel.org>
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| From | Adrian Hunter <adrian.hunter@intel.com> |
|---|---|
| Date | 2016-07-20 10:40 +0200 |
| Subject | Re: [PATCH 2/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder |
| Message-ID | <rWVcR-7sY-13@gated-at.bofh.it> |
| In reply to | #1446884 |
On 20/07/16 04:50, Masami Hiramatsu wrote: > On Tue, 19 Jul 2016 15:46:48 +0300 > Adrian Hunter <adrian.hunter@intel.com> wrote: > >> Add support for Intel's AVX-512 instructions to the instruction decoder. >> >> AVX-512 instructions are documented in Intel Architecture Instruction Set >> Extensions Programming Reference (February 2016). >> >> AVX-512 instructions are identifed by a EVEX prefix which, for the purpose >> of instruction decoding, can be treated as though it were a 4-byte VEX >> prefix. >> >> Existing instructions which can now accept an EVEX prefix need not be >> further annotated in the op code map (x86-opcode-map.txt). In the case of >> new instructions, the op code map is updated accordingly. >> >> Also add associated Mask Instructions that are used to manipulate mask >> registers used in AVX-512 instructions. >> >> Add a representative set of instructions to the perf tools new instructons >> test. > > Hmm, could you split this patch into 2 or 3 parts for review? > One is for core-kernel, the others are for perf tools (feature > adding and tests). > > [..] >> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt >> index 28082de46f0d..92b89fa5f414 100644 >> --- a/arch/x86/lib/x86-opcode-map.txt >> +++ b/arch/x86/lib/x86-opcode-map.txt >> @@ -13,12 +13,17 @@ >> # opcode: escape # escaped-name >> # EndTable >> # >> +# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix >> +# mnemonics that begin with lowercase 'k' accept a VEX prefix >> +# > > Ah, nice :) > >> #<group maps> >> # GrpTable: GrpXXX >> # reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...] >> # EndTable >> # >> # AVX Superscripts >> +# (ev): this opcode requires EVEX prefix. >> +# (evo): this opcode accepts EVEX prefix. > > Hmm, what the 'o' stands for? I thought it means "EVEX ONLY", but the comment is > opposite. For example, see 'o64', which means "64bit only". > And anyway, as you said above, if all existing instructions can accept EVEX prefix, > why would we need it? > >> -5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) >> +5b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) > > Ah, I see, so that is for the instructions which change the mnemonic since > byte-width is changed... > > OK, so please update the above description of the superscript, like as > "this opcode is changed by EVEX prefix (EVEX opcode)" etc. > > Thank you, > > Thanks for your quick reply. I have updated the patches as you requested and sent V2.
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