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[PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

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  [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver  Tai Nguyen <ttnguyen@apm.com> - 2016-07-11 21:10 +0200
    [PATCH v8 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Tai Nguyen <ttnguyen@apm.com> - 2016-07-11 21:10 +0200
    Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring  Unit driver Will Deacon <will.deacon@arm.com> - 2016-07-14 15:20 +0200
      Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring  Unit driver Tai Tri Nguyen <ttnguyen@apm.com> - 2016-07-14 19:30 +0200
        Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring  Unit driver Duc Dang <dhdang@apm.com> - 2016-07-14 19:40 +0200
          Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring  Unit driver Duc Dang <dhdang@apm.com> - 2016-07-19 22:30 +0200
            Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring  Unit driver Will Deacon <will.deacon@arm.com> - 2016-07-20 12:20 +0200
              Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring  Unit driver Duc Dang <dhdang@apm.com> - 2016-07-20 20:10 +0200

#1440828 — [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
memory controller bridges and memory. These PMU devices are loosely
architected to follow the same model as the PMU for ARM cores.

Signed-off-by: Tai Nguyen <ttnguyen@apm.com>
---

v8:
 * MAINTAINERS: Fix section header in one line
 * Change module_platform_driver to builtin_platform_driver
   Get rid of the use of module.h and its no-ops macros

v7:
 * Remove const from the definition of xgene_pmu_cpumask_attrs
 * Validate the event group as a whole, disallow creating groups containing
   mixed PMUs
 * Implement pmu::pmu_enable() and pmu::pmu_disable() to let the perf core
   starts and stops the counters properly
 * Using list_for_each_entry() instead of list_for_each_entry_safe() to iterate
   over the list of pmu sub-devices
 * Fix resource leak issue in case of registering perf devices fails
 * Pass on returned error if acpi_walk_namespace() fails
 * Remove unused xgene_pmu_data::data
 * Move enable interrupt after probing pmu sub-devices

v6:
 * Add IRQF_NOBALANCING and IRQF_NO_THREAD flags to the PMU overflow interrupt
   Exclude the interrupt from irq balancing and prevent the context from being
   threaded

v5:
 * Remove hw_perf_event::extra_reg field use
   Change GET_CNTR to use hw_perf_event::idx
   Change GET_AGENTID/GET_AGEN1ID to use hw_perf_event::config_base
 * Use compound literal structure defines for format and event attribute groups
   to statically define them at compile time
 * Bitwise invert the meaning of agent mask in config1 field.
 * Fix update pmu_counter_event pointer before starting event
 * Add reset of pmu_dev->pmu_counter_event to NULL in xgene_perf_del
 * Use exactly half of max period to fix the overflow counter issue and account
   for the possiblity of extreme interrupt latency
 * Use spin lock instead of interrupt masking in overflow interrupt handler
 * Remove unnecessary update of hw_perf_event::period_left

v4:
 * Alphabetically sorting header files
 * Remove dynamic allocation for PMU format and event attribute groups
   Create shared constant attribute groups per each class
 * Remove perf_sample_data as this perf driver doesn't support sampling
 * Consistently use the PCP_PMU_V{1,2} defines
 * Set affinity to make sure the overflow interrupt is handled by the
   same assigned CPU

v3:
 * Remove index property use in PMU device sub nodes

v2:
 * Use bitmask for event asignned counter mask pmu_dev->cntr_assign_mask
 * Remove unnecessary spinlocks in perf add/del operations
 * Remove unnecessary condition checks
 * Enforce CPU assignment to one CPU for perf operarations
 * Set the task_ctx_nr to perf_invalid_context for perf driver
 * Remove irrelevant pt_rregs
 * Change perf sysfs attributes to be fixed instead of dynamic
 * Fix checking for an ACPI companion device instead of EFI enable
 * Add documentation for config/config1 fields format and perf tool example

---

Tai Nguyen (4):
  MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
  Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
  perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
  arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries

 .../devicetree/bindings/perf/apm-xgene-pmu.txt     |  112 ++
 Documentation/perf/xgene-pmu.txt                   |   48 +
 MAINTAINERS                                        |    7 +
 arch/arm64/boot/dts/apm/apm-storm.dtsi             |   58 +
 drivers/perf/Kconfig                               |    7 +
 drivers/perf/Makefile                              |    1 +
 drivers/perf/xgene_pmu.c                           | 1392 ++++++++++++++++++++
 7 files changed, 1625 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
 create mode 100644 Documentation/perf/xgene-pmu.txt
 create mode 100644 drivers/perf/xgene_pmu.c

-- 
1.9.1

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#1440830 — [PATCH v8 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding

Signed-off-by: Tai Nguyen <ttnguyen@apm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/perf/apm-xgene-pmu.txt     | 112 +++++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt

diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
new file mode 100644
index 0000000..afb11cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
@@ -0,0 +1,112 @@
+* APM X-Gene SoC PMU bindings
+
+This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
+The following PMU devices are supported:
+
+  L3C			- L3 cache controller
+  IOB			- IO bridge
+  MCB			- Memory controller bridge
+  MC			- Memory controller
+
+The following section describes the SoC PMU DT node binding.
+
+Required properties:
+- compatible		: Shall be "apm,xgene-pmu" for revision 1 or
+                          "apm,xgene-pmu-v2" for revision 2.
+- regmap-csw		: Regmap of the CPU switch fabric (CSW) resource.
+- regmap-mcba		: Regmap of the MCB-A (memory bridge) resource.
+- regmap-mcbb		: Regmap of the MCB-B (memory bridge) resource.
+- reg			: First resource shall be the CPU bus PMU resource.
+- interrupts            : Interrupt-specifier for PMU IRQ.
+
+Required properties for L3C subnode:
+- compatible		: Shall be "apm,xgene-pmu-l3c".
+- reg			: First resource shall be the L3C PMU resource.
+
+Required properties for IOB subnode:
+- compatible		: Shall be "apm,xgene-pmu-iob".
+- reg			: First resource shall be the IOB PMU resource.
+
+Required properties for MCB subnode:
+- compatible		: Shall be "apm,xgene-pmu-mcb".
+- reg			: First resource shall be the MCB PMU resource.
+- enable-bit-index	: The bit indicates if the according MCB is enabled.
+
+Required properties for MC subnode:
+- compatible		: Shall be "apm,xgene-pmu-mc".
+- reg			: First resource shall be the MC PMU resource.
+- enable-bit-index	: The bit indicates if the according MC is enabled.
+
+Example:
+	csw: csw@7e200000 {
+		compatible = "apm,xgene-csw", "syscon";
+		reg = <0x0 0x7e200000 0x0 0x1000>;
+	};
+
+	mcba: mcba@7e700000 {
+		compatible = "apm,xgene-mcb", "syscon";
+		reg = <0x0 0x7e700000 0x0 0x1000>;
+	};
+
+	mcbb: mcbb@7e720000 {
+		compatible = "apm,xgene-mcb", "syscon";
+		reg = <0x0 0x7e720000 0x0 0x1000>;
+	};
+
+	pmu: pmu@78810000 {
+		compatible = "apm,xgene-pmu-v2";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		regmap-csw = <&csw>;
+		regmap-mcba = <&mcba>;
+		regmap-mcbb = <&mcbb>;
+		reg = <0x0 0x78810000 0x0 0x1000>;
+		interrupts = <0x0 0x22 0x4>;
+
+		pmul3c@7e610000 {
+			compatible = "apm,xgene-pmu-l3c";
+			reg = <0x0 0x7e610000 0x0 0x1000>;
+		};
+
+		pmuiob@7e940000 {
+			compatible = "apm,xgene-pmu-iob";
+			reg = <0x0 0x7e940000 0x0 0x1000>;
+		};
+
+		pmucmcb@7e710000 {
+			compatible = "apm,xgene-pmu-mcb";
+			reg = <0x0 0x7e710000 0x0 0x1000>;
+			enable-bit-index = <0>;
+		};
+
+		pmucmcb@7e730000 {
+			compatible = "apm,xgene-pmu-mcb";
+			reg = <0x0 0x7e730000 0x0 0x1000>;
+			enable-bit-index = <1>;
+		};
+
+		pmucmc@7e810000 {
+			compatible = "apm,xgene-pmu-mc";
+			reg = <0x0 0x7e810000 0x0 0x1000>;
+			enable-bit-index = <0>;
+		};
+
+		pmucmc@7e850000 {
+			compatible = "apm,xgene-pmu-mc";
+			reg = <0x0 0x7e850000 0x0 0x1000>;
+			enable-bit-index = <1>;
+		};
+
+		pmucmc@7e890000 {
+			compatible = "apm,xgene-pmu-mc";
+			reg = <0x0 0x7e890000 0x0 0x1000>;
+			enable-bit-index = <2>;
+		};
+
+		pmucmc@7e8d0000 {
+			compatible = "apm,xgene-pmu-mc";
+			reg = <0x0 0x7e8d0000 0x0 0x1000>;
+			enable-bit-index = <3>;
+		};
+	};
-- 
1.9.1

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#1443445 — Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
> memory controller bridges and memory. These PMU devices are loosely
> architected to follow the same model as the PMU for ARM cores.

You might want to add commit messages to patches 1,2 and 4, but then you
can route this via the arm-soc tree.

Will

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#1443623 — Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

Hi Will,

On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon <will.deacon@arm.com> wrote:
> On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
>> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
>> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
>> memory controller bridges and memory. These PMU devices are loosely
>> architected to follow the same model as the PMU for ARM cores.
>
> You might want to add commit messages to patches 1,2 and 4, but then you
> can route this via the arm-soc tree.
>
> Will

I will add the commit messages to these patches 1, 2 and 4 and rout
this via arm-soc tree.
CC: Duc (dhdang@apm.com)

Thanks,
-- 
Tai

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#1443625 — Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen <ttnguyen@apm.com> wrote:
>
> Hi Will,
>
> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon <will.deacon@arm.com> wrote:
> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
> >> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
> >> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
> >> memory controller bridges and memory. These PMU devices are loosely
> >> architected to follow the same model as the PMU for ARM cores.
> >
> > You might want to add commit messages to patches 1,2 and 4, but then you
> > can route this via the arm-soc tree.
> >
> > Will
>
> I will add the commit messages to these patches 1, 2 and 4 and rout
> this via arm-soc tree.
> CC: Duc (dhdang@apm.com)

I will pull patch 1, 2 and 4 into xgene-next tree and send pull
request to Arnd and Olof.

>
> Thanks,
> --
> Tai
Regards,
Duc Dang.

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#1446708 — Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang <dhdang@apm.com> wrote:
> On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen <ttnguyen@apm.com> wrote:
>>
>> Hi Will,
>>
>> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon <will.deacon@arm.com> wrote:
>> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
>> >> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
>> >> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
>> >> memory controller bridges and memory. These PMU devices are loosely
>> >> architected to follow the same model as the PMU for ARM cores.
>> >
>> > You might want to add commit messages to patches 1,2 and 4, but then you
>> > can route this via the arm-soc tree.
>> >
>> > Will
>>
>> I will add the commit messages to these patches 1, 2 and 4 and rout
>> this via arm-soc tree.
>> CC: Duc (dhdang@apm.com)
>
> I will pull patch 1, 2 and 4 into xgene-next tree and send pull
> request to Arnd and Olof.

Hi Will,

Do you plan to merge this series (Tai posted v10) into 4.8 or you want
to wait until 4.9? Please let know so that I can plan my pull request
to Arnd/Olof accordingly to include patch 1, 2, and 4.

Regards,
Duc Dang.
>
>>
>> Thanks,
>> --
>> Tai
> Regards,
> Duc Dang.

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#1447143 — Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

On Tue, Jul 19, 2016 at 01:22:09PM -0700, Duc Dang wrote:
> On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang <dhdang@apm.com> wrote:
> > On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen <ttnguyen@apm.com> wrote:
> >> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon <will.deacon@arm.com> wrote:
> >> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
> >> >> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
> >> >> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
> >> >> memory controller bridges and memory. These PMU devices are loosely
> >> >> architected to follow the same model as the PMU for ARM cores.
> >> >
> >> > You might want to add commit messages to patches 1,2 and 4, but then you
> >> > can route this via the arm-soc tree.
> >> >
> >> > Will
> >>
> >> I will add the commit messages to these patches 1, 2 and 4 and rout
> >> this via arm-soc tree.
> >> CC: Duc (dhdang@apm.com)
> >
> > I will pull patch 1, 2 and 4 into xgene-next tree and send pull
> > request to Arnd and Olof.
> 
> Hi Will,
> 
> Do you plan to merge this series (Tai posted v10) into 4.8 or you want
> to wait until 4.9? Please let know so that I can plan my pull request
> to Arnd/Olof accordingly to include patch 1, 2, and 4.

I was hoping that the whole series would go via arm-soc. Mark reviewed
the PMU driver code, so that should be sufficient.

Will

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#1447386 — Re: [PATCH v8 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver

On Wed, Jul 20, 2016 at 3:15 AM, Will Deacon <will.deacon@arm.com> wrote:
> On Tue, Jul 19, 2016 at 01:22:09PM -0700, Duc Dang wrote:
>> On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang <dhdang@apm.com> wrote:
>> > On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen <ttnguyen@apm.com> wrote:
>> >> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon <will.deacon@arm.com> wrote:
>> >> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
>> >> >> In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there
>> >> >> are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s),
>> >> >> memory controller bridges and memory. These PMU devices are loosely
>> >> >> architected to follow the same model as the PMU for ARM cores.
>> >> >
>> >> > You might want to add commit messages to patches 1,2 and 4, but then you
>> >> > can route this via the arm-soc tree.
>> >> >
>> >> > Will
>> >>
>> >> I will add the commit messages to these patches 1, 2 and 4 and rout
>> >> this via arm-soc tree.
>> >> CC: Duc (dhdang@apm.com)
>> >
>> > I will pull patch 1, 2 and 4 into xgene-next tree and send pull
>> > request to Arnd and Olof.
>>
>> Hi Will,
>>
>> Do you plan to merge this series (Tai posted v10) into 4.8 or you want
>> to wait until 4.9? Please let know so that I can plan my pull request
>> to Arnd/Olof accordingly to include patch 1, 2, and 4.
>
> I was hoping that the whole series would go via arm-soc. Mark reviewed
> the PMU driver code, so that should be sufficient.

Thanks, Will.

Hi Arnd, Olof,

Can you please help merge v10 of this series into your arm-soc tree? I
can merge this series into xgene-next and send a pull request to you
too, but the pull request will only contain this series as I don't
have more dts changes at this time.

Regards,
Duc Dang.
>
> Will

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