Groups > linux.kernel > #1438213 > unrolled thread

[GIT PULL v2] STi SoC changes for v4.8

Started by	Patrice Chotard <patrice.chotard@st.com>
First post	2016-07-07 09:20 +0200
Last post	2016-07-07 15:30 +0200
Articles	2 — 2 participants

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  [GIT PULL v2] STi SoC changes for v4.8 Patrice Chotard <patrice.chotard@st.com> - 2016-07-07 09:20 +0200
    Re: [GIT PULL v2] STi SoC changes for v4.8 Arnd Bergmann <arnd@arndb.de> - 2016-07-07 15:30 +0200

#1438213 — [GIT PULL v2] STi SoC changes for v4.8

From	Patrice Chotard <patrice.chotard@st.com>
Date	2016-07-07 09:20 +0200
Subject	[GIT PULL v2] STi SoC changes for v4.8
Message-ID	<rSbLk-3Kd-19@gated-at.bofh.it>

The following changes since commit 4c2e07c6a29e0129e975727b9f57eede813eea85:

   Linux 4.7-rc5 (2016-06-26 17:52:03 -0700)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git 
tags/sti-soc-for-v4.8

for you to fetch changes up to 55aa35180c57d82f3db23e5aabce97acb0d36681:

   ARM: sti: Implement dummy L2 cache's write_sec (2016-07-01 16:23:44 
+0200)

----------------------------------------------------------------

Highlights:
-----------
- Add a dummy L2 cache's write_sec callback as in non secure mode execution,
   we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a
   more generic for the STi SoCs family

----------------------------------------------------------------
Patrice Chotard (1):
       ARM: sti: Implement dummy L2 cache's write_sec

Peter Griffin (1):
       ARM: STi: Update machine _namestr to be more generic.

  arch/arm/mach-sti/board-dt.c | 11 ++++++++++-
  1 file changed, 10 insertions(+), 1 deletion(-)

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#1438620

From	Arnd Bergmann <arnd@arndb.de>
Date	2016-07-07 15:30 +0200
Message-ID	<rShxo-7rQ-17@gated-at.bofh.it>
In reply to	#1438213

On Thursday, July 7, 2016 9:16:05 AM CEST Patrice Chotard wrote:
> Highlights:
> -----------
> - Add a dummy L2 cache's write_sec callback as in non secure mode execution,
>    we can't get access to L2 cache secure registers
> - Cosmetics change, in case of dump_stack, update the hardware name with a
>    more generic for the STi SoCs family
> 

This is also based on -rc5, please send a third version rebased to -rc3 or
earlier.

	Arnd

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[GIT PULL v2] STi SoC changes for v4.8

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#1438213 — [GIT PULL v2] STi SoC changes for v4.8

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