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| Started by | Patrice Chotard <patrice.chotard@st.com> |
|---|---|
| First post | 2016-07-01 16:50 +0200 |
| Last post | 2016-07-07 09:20 +0200 |
| Articles | 3 — 2 participants |
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[GIT PULL] STi SoC changes for v4.8 Patrice Chotard <patrice.chotard@st.com> - 2016-07-01 16:50 +0200
Re: [GIT PULL] STi SoC changes for v4.8 Olof Johansson <olof@lixom.net> - 2016-07-07 07:50 +0200
Re: [GIT PULL] STi SoC changes for v4.8 Patrice Chotard <patrice.chotard@st.com> - 2016-07-07 09:20 +0200
| From | Patrice Chotard <patrice.chotard@st.com> |
|---|---|
| Date | 2016-07-01 16:50 +0200 |
| Subject | [GIT PULL] STi SoC changes for v4.8 |
| Message-ID | <rQ7Vv-7Qe-1@gated-at.bofh.it> |
Hi Olof, Arnd and Kevin,
Please consider this first round of STi SoC updates for v4.8:
The following changes since commit
4c2e07c6a29e0129e975727b9f57eede813eea85:
Linux 4.7-rc5 (2016-06-26 17:52:03 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git
sti-soc_for_v4.8
for you to fetch changes up to 55aa35180c57d82f3db23e5aabce97acb0d36681:
ARM: sti: Implement dummy L2 cache's write_sec (2016-07-01 16:23:44
+0200)
----------------------------------------------------------------
Highlights:
-----------
_ add a dummy L2 cache's write_sec callback as in non secure mode
execution,
we can't get access to L2 cache secure registers
_ cosmetics change, in case of dump_stack, update the hardware name with a
more genericfor the STi SoCs family
----------------------------------------------------------------
Patrice Chotard (1):
ARM: sti: Implement dummy L2 cache's write_sec
Peter Griffin (1):
ARM: STi: Update machine _namestr to be more generic.
arch/arm/mach-sti/board-dt.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
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| From | Olof Johansson <olof@lixom.net> |
|---|---|
| Date | 2016-07-07 07:50 +0200 |
| Message-ID | <rSamd-2Gr-3@gated-at.bofh.it> |
| In reply to | #1435386 |
On Fri, Jul 01, 2016 at 04:47:46PM +0200, Patrice Chotard wrote: > Hi Olof, Arnd and Kevin, > > Please consider this first round of STi SoC updates for v4.8: > > The following changes since commit 4c2e07c6a29e0129e975727b9f57eede813eea85: > > Linux 4.7-rc5 (2016-06-26 17:52:03 -0700) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git > sti-soc_for_v4.8 Again, that's a branch and not a tag. > for you to fetch changes up to 55aa35180c57d82f3db23e5aabce97acb0d36681: > > ARM: sti: Implement dummy L2 cache's write_sec (2016-07-01 16:23:44 +0200) > ---------------------------------------------------------------- > > Highlights: > ----------- > _ add a dummy L2 cache's write_sec callback as in non secure mode execution, > we can't get access to L2 cache secure registers > _ cosmetics change, in case of dump_stack, update the hardware name with a > more genericfor the STi SoCs family Minor nit: This is a somewhat odd format to write a list in. Please use '-' or '*' instead, and feel free to use capital letters, etc. :) -Olof
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| From | Patrice Chotard <patrice.chotard@st.com> |
|---|---|
| Date | 2016-07-07 09:20 +0200 |
| Message-ID | <rSbLj-3Kd-5@gated-at.bofh.it> |
| In reply to | #1438183 |
Hi Olof On 07/07/2016 07:30 AM, Olof Johansson wrote: > On Fri, Jul 01, 2016 at 04:47:46PM +0200, Patrice Chotard wrote: >> Hi Olof, Arnd and Kevin, >> >> Please consider this first round of STi SoC updates for v4.8: >> >> The following changes since commit 4c2e07c6a29e0129e975727b9f57eede813eea85: >> >> Linux 4.7-rc5 (2016-06-26 17:52:03 -0700) >> >> are available in the git repository at: >> >> git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git >> sti-soc_for_v4.8 > Again, that's a branch and not a tag. Right, i will fix that > >> for you to fetch changes up to 55aa35180c57d82f3db23e5aabce97acb0d36681: >> >> ARM: sti: Implement dummy L2 cache's write_sec (2016-07-01 16:23:44 +0200) >> ---------------------------------------------------------------- >> >> Highlights: >> ----------- >> _ add a dummy L2 cache's write_sec callback as in non secure mode execution, >> we can't get access to L2 cache secure registers >> _ cosmetics change, in case of dump_stack, update the hardware name with a >> more genericfor the STi SoCs family > Minor nit: This is a somewhat odd format to write a list in. Please use > '-' or '*' instead, and feel free to use capital letters, etc. :) Thanks for reviewing, i will submit a v2 Patrice > > > -Olof
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