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[PATCH v2 0/3] Cache id

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  [PATCH v2 0/3] Cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-07-06 21:10 +0200
    [PATCH v2 1/3] cacheinfo: Introduce cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-07-06 21:10 +0200
    [PATCH v2 3/3] x86, intel_cacheinfo: Enable cache id in x86 "Fenghua Yu" <fenghua.yu@intel.com> - 2016-07-06 21:10 +0200
    Re: [PATCH v2 0/3] Cache id Borislav Petkov <bp@suse.de> - 2016-07-07 18:30 +0200
      RE: [PATCH v2 0/3] Cache id "Yu, Fenghua" <fenghua.yu@intel.com> - 2016-07-08 05:20 +0200

#1437915 — [PATCH v2 0/3] Cache id

From: Fenghua Yu <fenghua.yu@intel.com>

This patch set introduces cache id to identify a cache in platform. It can
be useful in such areas as Cach Allocation Technology (CAT) where user
needs to specify how much cache is allocated on which cache. Cache id
provides a concise way to identify the cache. CAT patches will be released
separately.

Changes:
v2: Split one patch into three patches and add ABI documentation.

Fenghua Yu (3):
  cacheinfo: Introduce cache id
  Documentation, ABI: Add a document entry for cache id
  x86, intel_cacheinfo: Enable cache id in x86

 Documentation/ABI/testing/sysfs-devices-system-cpu | 13 +++++++++++++
 arch/x86/kernel/cpu/intel_cacheinfo.c              | 20 ++++++++++++++++++++
 drivers/base/cacheinfo.c                           |  5 +++++
 include/linux/cacheinfo.h                          |  3 +++
 4 files changed, 41 insertions(+)

-- 
2.5.0

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#1437916 — [PATCH v2 1/3] cacheinfo: Introduce cache id

From: Fenghua Yu <fenghua.yu@intel.com>

Each cache is described by cacheinfo and is unique in the same index
across the platform. But there is no id for a cache. We introduce cache
ID to identify a cache.

Intel Cache Allocation Technology (CAT) allows some control on the
allocation policy within each cache that it controls. We need a unique
cache ID for each cache level to allow the user to specify which
controls are applied to which cache. Cache id is a concise way to specify
a cache.

Cache id is first enabled on x86. It can be enabled on other platforms
as well. The cache id is not necessary contiguous.

Add an "id" entry to /sys/devices/system/cpu/cpu*/cache/index*/

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 drivers/base/cacheinfo.c  | 5 +++++
 include/linux/cacheinfo.h | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index e9fd32e..2a21c15 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -233,6 +233,7 @@ static ssize_t file_name##_show(struct device *dev,		\
 	return sprintf(buf, "%u\n", this_leaf->object);		\
 }
 
+show_one(id, id);
 show_one(level, level);
 show_one(coherency_line_size, coherency_line_size);
 show_one(number_of_sets, number_of_sets);
@@ -314,6 +315,7 @@ static ssize_t write_policy_show(struct device *dev,
 	return n;
 }
 
+static DEVICE_ATTR_RO(id);
 static DEVICE_ATTR_RO(level);
 static DEVICE_ATTR_RO(type);
 static DEVICE_ATTR_RO(coherency_line_size);
@@ -327,6 +329,7 @@ static DEVICE_ATTR_RO(shared_cpu_list);
 static DEVICE_ATTR_RO(physical_line_partition);
 
 static struct attribute *cache_default_attrs[] = {
+	&dev_attr_id.attr,
 	&dev_attr_type.attr,
 	&dev_attr_level.attr,
 	&dev_attr_shared_cpu_map.attr,
@@ -350,6 +353,8 @@ cache_default_attrs_is_visible(struct kobject *kobj,
 	const struct cpumask *mask = &this_leaf->shared_cpu_map;
 	umode_t mode = attr->mode;
 
+	if ((attr == &dev_attr_id.attr) && this_leaf->attributes & CACHE_ID)
+		return mode;
 	if ((attr == &dev_attr_type.attr) && this_leaf->type)
 		return mode;
 	if ((attr == &dev_attr_level.attr) && this_leaf->level)
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 2189935..cf6984d 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -18,6 +18,7 @@ enum cache_type {
 
 /**
  * struct cacheinfo - represent a cache leaf node
+ * @id: This cache's id. ID is unique in the same index on the platform.
  * @type: type of the cache - data, inst or unified
  * @level: represents the hierarchy in the multi-level cache
  * @coherency_line_size: size of each cache line usually representing
@@ -44,6 +45,7 @@ enum cache_type {
  * keeping, the remaining members form the core properties of the cache
  */
 struct cacheinfo {
+	unsigned int id;
 	enum cache_type type;
 	unsigned int level;
 	unsigned int coherency_line_size;
@@ -61,6 +63,7 @@ struct cacheinfo {
 #define CACHE_WRITE_ALLOCATE	BIT(3)
 #define CACHE_ALLOCATE_POLICY_MASK	\
 	(CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE)
+#define CACHE_ID		BIT(4)
 
 	struct device_node *of_node;
 	bool disable_sysfs;
-- 
2.5.0

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#1437917 — [PATCH v2 3/3] x86, intel_cacheinfo: Enable cache id in x86

From: Fenghua Yu <fenghua.yu@intel.com>

Enable cache id in x86. Cache id comes from APIC ID and CPUID4.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index de6626c..8dc5720 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -153,6 +153,7 @@ struct _cpuid4_info_regs {
 	union _cpuid4_leaf_eax eax;
 	union _cpuid4_leaf_ebx ebx;
 	union _cpuid4_leaf_ecx ecx;
+	unsigned int id;
 	unsigned long size;
 	struct amd_northbridge *nb;
 };
@@ -894,6 +895,8 @@ static void __cache_cpumap_setup(unsigned int cpu, int index,
 static void ci_leaf_init(struct cacheinfo *this_leaf,
 			 struct _cpuid4_info_regs *base)
 {
+	this_leaf->id = base->id;
+	this_leaf->attributes = CACHE_ID;
 	this_leaf->level = base->eax.split.level;
 	this_leaf->type = cache_type_map[base->eax.split.type];
 	this_leaf->coherency_line_size =
@@ -920,6 +923,22 @@ static int __init_cache_level(unsigned int cpu)
 	return 0;
 }
 
+/*
+ * The max shared threads number comes from CPUID.4:EAX[25-14] with input
+ * ECX as cache index. Then right shift apicid by the number's order to get
+ * cache id for this cache node.
+ */
+static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4_regs)
+{
+	struct cpuinfo_x86 *c = &cpu_data(cpu);
+	unsigned long num_threads_sharing;
+	int index_msb;
+
+	num_threads_sharing = 1 + id4_regs->eax.split.num_threads_sharing;
+	index_msb = get_count_order(num_threads_sharing);
+	id4_regs->id = c->apicid >> index_msb;
+}
+
 static int __populate_cache_leaves(unsigned int cpu)
 {
 	unsigned int idx, ret;
@@ -931,6 +950,7 @@ static int __populate_cache_leaves(unsigned int cpu)
 		ret = cpuid4_cache_lookup_regs(idx, &id4_regs);
 		if (ret)
 			return ret;
+		get_cache_id(cpu, &id4_regs);
 		ci_leaf_init(this_leaf++, &id4_regs);
 		__cache_cpumap_setup(cpu, idx, &id4_regs);
 	}
-- 
2.5.0

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#1438714

On Wed, Jul 06, 2016 at 03:07:15PM -0700, Fenghua Yu wrote:
> From: Fenghua Yu <fenghua.yu@intel.com>
> 
> This patch set introduces cache id to identify a cache in platform. It can
> be useful in such areas as Cach Allocation Technology (CAT) where user
> needs to specify how much cache is allocated on which cache. Cache id
> provides a concise way to identify the cache. CAT patches will be released
> separately.
> 
> Changes:
> v2: Split one patch into three patches and add ABI documentation.
> 
> Fenghua Yu (3):
>   cacheinfo: Introduce cache id
>   Documentation, ABI: Add a document entry for cache id
>   x86, intel_cacheinfo: Enable cache id in x86
> 
>  Documentation/ABI/testing/sysfs-devices-system-cpu | 13 +++++++++++++
>  arch/x86/kernel/cpu/intel_cacheinfo.c              | 20 ++++++++++++++++++++
>  drivers/base/cacheinfo.c                           |  5 +++++
>  include/linux/cacheinfo.h                          |  3 +++
>  4 files changed, 41 insertions(+)

All 3:

Acked-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
-- 

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#1439082

> From: Borislav Petkov [mailto:bp@suse.de]
> Sent: Thursday, July 07, 2016 9:21 AM
> On Wed, Jul 06, 2016 at 03:07:15PM -0700, Fenghua Yu wrote:
> > From: Fenghua Yu <fenghua.yu@intel.com>
> >
> > This patch set introduces cache id to identify a cache in platform. It
> > can be useful in such areas as Cach Allocation Technology (CAT) where
> > user needs to specify how much cache is allocated on which cache.
> > Cache id provides a concise way to identify the cache. CAT patches
> > will be released separately.
> >
> > Changes:
> > v2: Split one patch into three patches and add ABI documentation.
> >
> > Fenghua Yu (3):
> >   cacheinfo: Introduce cache id
> >   Documentation, ABI: Add a document entry for cache id
> >   x86, intel_cacheinfo: Enable cache id in x86
> >
> >  Documentation/ABI/testing/sysfs-devices-system-cpu | 13
> +++++++++++++
> >  arch/x86/kernel/cpu/intel_cacheinfo.c              | 20
> ++++++++++++++++++++
> >  drivers/base/cacheinfo.c                           |  5 +++++
> >  include/linux/cacheinfo.h                          |  3 +++
> >  4 files changed, 41 insertions(+)
> 
> All 3:
> 
> Acked-by: Borislav Petkov <bp@suse.de>

That's great!

Is it possible to merge the patches to 4.8? Then I don't need to carry these patches with upcoming CAT enabling patches:)

Thanks.

-Fenghua

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