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| Started by | William Wu <william.wu@rock-chips.com> |
|---|---|
| First post | 2016-06-30 13:20 +0200 |
| Last post | 2016-07-01 05:00 +0200 |
| Articles | 3 — 2 participants |
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[PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk William Wu <william.wu@rock-chips.com> - 2016-06-30 13:20 +0200
Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk Rob Herring <robh@kernel.org> - 2016-07-01 05:00 +0200
Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk[Involving remittance information, please pay attention to the safety of property] William Wu <william.wu@rock-chips.com> - 2016-07-01 05:00 +0200
| From | William Wu <william.wu@rock-chips.com> |
|---|---|
| Date | 2016-06-30 13:20 +0200 |
| Subject | [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk |
| Message-ID | <rPIaJ-to-11@gated-at.bofh.it> |
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v5:
- None
Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)
Changes in v3:
- None
Changes in v2:
- None
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3/core.c | 5 +++++
drivers/usb/dwc3/core.h | 3 +++
3 files changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 34d13a5..bd5bef0 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -42,6 +42,8 @@ Optional properties:
- snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
a free-running PHY clock.
+ - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
+ from P0 to P1/P2/P3 without delay.
- snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
- snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
with an 8- or 16-bit interface. Value 0 select 8-bit
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index e880686..320a50f 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -449,6 +449,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->dis_u3_susphy_quirk)
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
+ if (dwc->dis_del_phy_power_chg_quirk)
+ reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
+
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
@@ -943,6 +946,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,dis_rxdet_inp3_quirk");
dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
"snps,dis_u2_freeclk_exists_quirk");
+ dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
+ "snps,dis_del_phy_power_chg_quirk");
dwc->phyif_utmi_quirk = device_property_read_bool(dev,
"snps,phyif_utmi_quirk");
device_property_read_u8(dev, "snps,phyif_utmi",
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cf6696c..55e136d 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -809,6 +809,8 @@ struct dwc3_scratchpad_array {
* @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
* in GUSB2PHYCFG, specify that USB2 PHY doesn't
* provide a free-running PHY clock.
+ * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
+ * change quirk.
* @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk
* @phyif_utmi: UTMI+ PHY interface value
* 0 - 8 bits
@@ -957,6 +959,7 @@ struct dwc3 {
unsigned dis_enblslpm_quirk:1;
unsigned dis_rxdet_inp3_quirk:1;
unsigned dis_u2_freeclk_exists_quirk:1;
+ unsigned dis_del_phy_power_chg_quirk:1;
unsigned phyif_utmi_quirk:1;
unsigned phyif_utmi:1;
--
1.9.1
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-07-01 05:00 +0200 |
| Message-ID | <rPWQq-11a-9@gated-at.bofh.it> |
| In reply to | #1434467 |
On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote: > Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, > which specifies whether disable delay PHY power change > from P0 to P1/P2/P3 when link state changing from U0 > to U1/U2/U3 respectively. > > Signed-off-by: William Wu <william.wu@rock-chips.com> > --- > Changes in v5: > - None > > Changes in v4: > - rebase on top of balbi testing/next, remove pdata (balbi) > > Changes in v3: > - None > > Changes in v2: > - None > > Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ > drivers/usb/dwc3/core.c | 5 +++++ > drivers/usb/dwc3/core.h | 3 +++ > 3 files changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt > index 34d13a5..bd5bef0 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt > @@ -42,6 +42,8 @@ Optional properties: > - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists > in GUSB2PHYCFG, specify that USB2 PHY doesn't provide > a free-running PHY clock. > + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power > + from P0 to P1/P2/P3 without delay. Use '-', not '_'. > - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface. > - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY > with an 8- or 16-bit interface. Value 0 select 8-bit
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| From | William Wu <william.wu@rock-chips.com> |
|---|---|
| Date | 2016-07-01 05:00 +0200 |
| Subject | Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk[Involving remittance information, please pay attention to the safety of property] |
| Message-ID | <rPWQq-11a-13@gated-at.bofh.it> |
| In reply to | #1434986 |
Dear Rob,
On 07/01/2016 10:38 AM, Rob Herring wrote:
> On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
>> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
>> which specifies whether disable delay PHY power change
>> from P0 to P1/P2/P3 when link state changing from U0
>> to U1/U2/U3 respectively.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - None
>>
>> Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
>> drivers/usb/dwc3/core.c | 5 +++++
>> drivers/usb/dwc3/core.h | 3 +++
>> 3 files changed, 10 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 34d13a5..bd5bef0 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -42,6 +42,8 @@ Optional properties:
>> - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>> in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>> a free-running PHY clock.
>> + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
>> + from P0 to P1/P2/P3 without delay.
> Use '-', not '_'.
OK, I'll fix it in next patch.
Thanks~:-)
Best regards,
William Wu
>
>> - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
>> - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
>> with an 8- or 16-bit interface. Value 0 select 8-bit
>
>
>
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