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[PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi

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  [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi megous@megous.com - 2016-06-23 21:40 +0200
    Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi Chen-Yu Tsai <wens@csie.org> - 2016-06-24 05:50 +0200
      Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi Ondřej Jirman <megous@megous.com> - 2016-06-25 01:00 +0200
        Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi Chen-Yu Tsai <wens@csie.org> - 2016-06-25 03:10 +0200
          Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-06-25 09:10 +0200
            Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi Ondřej Jirman <megous@megous.com> - 2016-06-25 17:00 +0200
              Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-06-29 22:50 +0200
                Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi Ondřej Jirman <megous@megous.com> - 2016-06-29 23:20 +0200
                  Re: [linux-sunxi] Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label  to sun8i-h3.dtsi Michal Suchanek <hramrach@gmail.com> - 2016-06-30 13:10 +0200
                    Re: [linux-sunxi] Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label  to sun8i-h3.dtsi Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-06-30 22:50 +0200

#1430095 — [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi

From: Ondrej Jirman <megous@megous.com>

Add label to the first cpu so that it can be referenced
from derived dts files.

Signed-off-by: Ondrej Jirman <megous@megous.com>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 9938972..82faefc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -52,7 +52,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
-- 
2.9.0

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#1430333

On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> Add label to the first cpu so that it can be referenced
> from derived dts files.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 9938972..82faefc 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -52,7 +52,7 @@
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>
> -               cpu@0 {
> +               cpu0: cpu@0 {
>                         compatible = "arm,cortex-a7";
>                         device_type = "cpu";
>                         reg = <0>;

Can you also set the cpu clock here? It is part of the SoC
and does not belong in the board DTS files.

Otherwise this one looks good.

ChenYu

> --
> 2.9.0
>

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#1430993

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Hello,

comments below.

On 24.6.2016 05:48, Chen-Yu Tsai wrote:
> On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
>> From: Ondrej Jirman <megous@megous.com>
>>
>> Add label to the first cpu so that it can be referenced
>> from derived dts files.
>>
>> Signed-off-by: Ondrej Jirman <megous@megous.com>
>> ---
>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>> index 9938972..82faefc 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -52,7 +52,7 @@
>>                 #address-cells = <1>;
>>                 #size-cells = <0>;
>>
>> -               cpu@0 {
>> +               cpu0: cpu@0 {
>>                         compatible = "arm,cortex-a7";
>>                         device_type = "cpu";
>>                         reg = <0>;
> 
> Can you also set the cpu clock here? It is part of the SoC
> and does not belong in the board DTS files.

Do you mean operating-points, or something else? Different SBCs will
probably require different combinations of operating points just for
safety's sake, because they have different regulators and [some have
botched] thermal designs, so it might make sense to customize it for
differnt boards, and I don't feel adventurous enough setting it for all
H3 boards out there.

Or is this comment related to the missing cpu clock rate message I see
on every boot?

[    0.058912] /cpus/cpu@0 missing clock-frequency property

regards,
  Ondrej

> Otherwise this one looks good.
> 
> ChenYu
> 
>> --
>> 2.9.0
>>

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#1431034

On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <megous@megous.com> wrote:
> Hello,
>
> comments below.
>
> On 24.6.2016 05:48, Chen-Yu Tsai wrote:
>> On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
>>> From: Ondrej Jirman <megous@megous.com>
>>>
>>> Add label to the first cpu so that it can be referenced
>>> from derived dts files.
>>>
>>> Signed-off-by: Ondrej Jirman <megous@megous.com>
>>> ---
>>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>>> index 9938972..82faefc 100644
>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>>> @@ -52,7 +52,7 @@
>>>                 #address-cells = <1>;
>>>                 #size-cells = <0>;
>>>
>>> -               cpu@0 {
>>> +               cpu0: cpu@0 {
>>>                         compatible = "arm,cortex-a7";
>>>                         device_type = "cpu";
>>>                         reg = <0>;
>>
>> Can you also set the cpu clock here? It is part of the SoC
>> and does not belong in the board DTS files.
>
> Do you mean operating-points, or something else? Different SBCs will
> probably require different combinations of operating points just for
> safety's sake, because they have different regulators and [some have
> botched] thermal designs, so it might make sense to customize it for
> differnt boards, and I don't feel adventurous enough setting it for all
> H3 boards out there.

I meant clocks = <...> and clock-latency = <...>.

These 2 are part of the SoC.

The OPP can stay in the board files. It's a pity there's no standard
OPP table for H3 though. :(

ChenYu

>
> Or is this comment related to the missing cpu clock rate message I see
> on every boot?
>
> [    0.058912] /cpus/cpu@0 missing clock-frequency property
>
> regards,
>   Ondrej
>
>> Otherwise this one looks good.
>>
>> ChenYu
>>
>>> --
>>> 2.9.0
>>>
>

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#1431070

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On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <megous@megous.com> wrote:
> > Hello,
> >
> > comments below.
> >
> > On 24.6.2016 05:48, Chen-Yu Tsai wrote:
> >> On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
> >>> From: Ondrej Jirman <megous@megous.com>
> >>>
> >>> Add label to the first cpu so that it can be referenced
> >>> from derived dts files.
> >>>
> >>> Signed-off-by: Ondrej Jirman <megous@megous.com>
> >>> ---
> >>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> >>> index 9938972..82faefc 100644
> >>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> >>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> >>> @@ -52,7 +52,7 @@
> >>>                 #address-cells = <1>;
> >>>                 #size-cells = <0>;
> >>>
> >>> -               cpu@0 {
> >>> +               cpu0: cpu@0 {
> >>>                         compatible = "arm,cortex-a7";
> >>>                         device_type = "cpu";
> >>>                         reg = <0>;
> >>
> >> Can you also set the cpu clock here? It is part of the SoC
> >> and does not belong in the board DTS files.
> >
> > Do you mean operating-points, or something else? Different SBCs will
> > probably require different combinations of operating points just for
> > safety's sake, because they have different regulators and [some have
> > botched] thermal designs, so it might make sense to customize it for
> > differnt boards, and I don't feel adventurous enough setting it for all
> > H3 boards out there.
> 
> I meant clocks = <...> and clock-latency = <...>.
> 
> These 2 are part of the SoC.
> 
> The OPP can stay in the board files. It's a pity there's no standard
> OPP table for H3 though. :(

This has never been the case, and we always had some deviation in the
FEX files for all the SoCs.

If we could come up with standard OPPs that work for every one,
there's no reason it can't happen here.

I don't really see why the thermal design should change anything. If a
boards heats faster, it will throttle down to a lower OPP faster, but
those OPPs are not going to change.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1431137

On 25.6.2016 09:02, Maxime Ripard wrote:
> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <megous@megous.com> wrote:
>>> Hello,
>>>
>>> comments below.
>>>
>>> On 24.6.2016 05:48, Chen-Yu Tsai wrote:
>>>> On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
>>>>> From: Ondrej Jirman <megous@megous.com>
>>>>>
>>>>> Add label to the first cpu so that it can be referenced
>>>>> from derived dts files.
>>>>>
>>>>> Signed-off-by: Ondrej Jirman <megous@megous.com>
>>>>> ---
>>>>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>> index 9938972..82faefc 100644
>>>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>> @@ -52,7 +52,7 @@
>>>>>                 #address-cells = <1>;
>>>>>                 #size-cells = <0>;
>>>>>
>>>>> -               cpu@0 {
>>>>> +               cpu0: cpu@0 {
>>>>>                         compatible = "arm,cortex-a7";
>>>>>                         device_type = "cpu";
>>>>>                         reg = <0>;
>>>>
>>>> Can you also set the cpu clock here? It is part of the SoC
>>>> and does not belong in the board DTS files.
>>>
>>> Do you mean operating-points, or something else? Different SBCs will
>>> probably require different combinations of operating points just for
>>> safety's sake, because they have different regulators and [some have
>>> botched] thermal designs, so it might make sense to customize it for
>>> differnt boards, and I don't feel adventurous enough setting it for all
>>> H3 boards out there.
>>
>> I meant clocks = <...> and clock-latency = <...>.
>>
>> These 2 are part of the SoC.
>>
>> The OPP can stay in the board files. It's a pity there's no standard
>> OPP table for H3 though. :(
> 
> This has never been the case, and we always had some deviation in the
> FEX files for all the SoCs.
> 
> If we could come up with standard OPPs that work for every one,
> there's no reason it can't happen here.
> 
> I don't really see why the thermal design should change anything. If a
> boards heats faster, it will throttle down to a lower OPP faster, but
> those OPPs are not going to change.

I've no way to test, but I've been told some Sinovoip boards are really
bad in this regard (SoC is not even well thermally connected to the
PCB/PCB not having copper layer to spread the heat). Thermal sensor
readings happen at fixed intervals, so the question is if you can heat
up the soc from say 80°C (first trip point) to over 110°C in less than
that period (330ms currently).

I say it shouldn't be a problem, if that small thing is drawing say 2W
at max load. It will burn or trigger a second trip point before the
first one has a chance to trigger and the kernel will shut down. I
remember tkaiser saying that he has to run that board at 240MHz max. But
perhaps I'm misremembering.

I'm just speculating.

regards,
  Ondrej



> Maxime
> 

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#1434044

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Hi,

On Sat, Jun 25, 2016 at 04:50:24PM +0200, Ondřej Jirman wrote:
> On 25.6.2016 09:02, Maxime Ripard wrote:
> > On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
> >> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <megous@megous.com> wrote:
> >>> Hello,
> >>>
> >>> comments below.
> >>>
> >>> On 24.6.2016 05:48, Chen-Yu Tsai wrote:
> >>>> On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
> >>>>> From: Ondrej Jirman <megous@megous.com>
> >>>>>
> >>>>> Add label to the first cpu so that it can be referenced
> >>>>> from derived dts files.
> >>>>>
> >>>>> Signed-off-by: Ondrej Jirman <megous@megous.com>
> >>>>> ---
> >>>>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
> >>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> >>>>> index 9938972..82faefc 100644
> >>>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> >>>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> >>>>> @@ -52,7 +52,7 @@
> >>>>>                 #address-cells = <1>;
> >>>>>                 #size-cells = <0>;
> >>>>>
> >>>>> -               cpu@0 {
> >>>>> +               cpu0: cpu@0 {
> >>>>>                         compatible = "arm,cortex-a7";
> >>>>>                         device_type = "cpu";
> >>>>>                         reg = <0>;
> >>>>
> >>>> Can you also set the cpu clock here? It is part of the SoC
> >>>> and does not belong in the board DTS files.
> >>>
> >>> Do you mean operating-points, or something else? Different SBCs will
> >>> probably require different combinations of operating points just for
> >>> safety's sake, because they have different regulators and [some have
> >>> botched] thermal designs, so it might make sense to customize it for
> >>> differnt boards, and I don't feel adventurous enough setting it for all
> >>> H3 boards out there.
> >>
> >> I meant clocks = <...> and clock-latency = <...>.
> >>
> >> These 2 are part of the SoC.
> >>
> >> The OPP can stay in the board files. It's a pity there's no standard
> >> OPP table for H3 though. :(
> > 
> > This has never been the case, and we always had some deviation in the
> > FEX files for all the SoCs.
> > 
> > If we could come up with standard OPPs that work for every one,
> > there's no reason it can't happen here.
> > 
> > I don't really see why the thermal design should change anything. If a
> > boards heats faster, it will throttle down to a lower OPP faster, but
> > those OPPs are not going to change.
> 
> I've no way to test, but I've been told some Sinovoip boards are really
> bad in this regard (SoC is not even well thermally connected to the
> PCB/PCB not having copper layer to spread the heat). Thermal sensor
> readings happen at fixed intervals, so the question is if you can heat
> up the soc from say 80°C (first trip point) to over 110°C in less than
> that period (330ms currently).
> 
> I say it shouldn't be a problem, if that small thing is drawing say 2W
> at max load. It will burn or trigger a second trip point before the
> first one has a chance to trigger and the kernel will shut down. I
> remember tkaiser saying that he has to run that board at 240MHz max. But
> perhaps I'm misremembering.
> 
> I'm just speculating.

Yes, but that's just poor thermal design. What I was saying is that
even if we really need to throttle the SoC to 240 MHz on that board
because it heats too much, the couple of the frequency and the voltage
will likely be the same across all boards. It's just the amount of
time we'll spend using it that will differ.

But that's just my understanding, I might be speaking non-sense :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1434053

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On 29.6.2016 22:45, Maxime Ripard wrote:
> Hi,
> 
> On Sat, Jun 25, 2016 at 04:50:24PM +0200, Ondřej Jirman wrote:
>> On 25.6.2016 09:02, Maxime Ripard wrote:
>>> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>>>> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <megous@megous.com> wrote:
>>>>> Hello,
>>>>>
>>>>> comments below.
>>>>>
>>>>> On 24.6.2016 05:48, Chen-Yu Tsai wrote:
>>>>>> On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
>>>>>>> From: Ondrej Jirman <megous@megous.com>
>>>>>>>
>>>>>>> Add label to the first cpu so that it can be referenced
>>>>>>> from derived dts files.
>>>>>>>
>>>>>>> Signed-off-by: Ondrej Jirman <megous@megous.com>
>>>>>>> ---
>>>>>>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>>>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>>>> index 9938972..82faefc 100644
>>>>>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>>>> @@ -52,7 +52,7 @@
>>>>>>>                 #address-cells = <1>;
>>>>>>>                 #size-cells = <0>;
>>>>>>>
>>>>>>> -               cpu@0 {
>>>>>>> +               cpu0: cpu@0 {
>>>>>>>                         compatible = "arm,cortex-a7";
>>>>>>>                         device_type = "cpu";
>>>>>>>                         reg = <0>;
>>>>>>
>>>>>> Can you also set the cpu clock here? It is part of the SoC
>>>>>> and does not belong in the board DTS files.
>>>>>
>>>>> Do you mean operating-points, or something else? Different SBCs will
>>>>> probably require different combinations of operating points just for
>>>>> safety's sake, because they have different regulators and [some have
>>>>> botched] thermal designs, so it might make sense to customize it for
>>>>> differnt boards, and I don't feel adventurous enough setting it for all
>>>>> H3 boards out there.
>>>>
>>>> I meant clocks = <...> and clock-latency = <...>.
>>>>
>>>> These 2 are part of the SoC.
>>>>
>>>> The OPP can stay in the board files. It's a pity there's no standard
>>>> OPP table for H3 though. :(
>>>
>>> This has never been the case, and we always had some deviation in the
>>> FEX files for all the SoCs.
>>>
>>> If we could come up with standard OPPs that work for every one,
>>> there's no reason it can't happen here.
>>>
>>> I don't really see why the thermal design should change anything. If a
>>> boards heats faster, it will throttle down to a lower OPP faster, but
>>> those OPPs are not going to change.
>>
>> I've no way to test, but I've been told some Sinovoip boards are really
>> bad in this regard (SoC is not even well thermally connected to the
>> PCB/PCB not having copper layer to spread the heat). Thermal sensor
>> readings happen at fixed intervals, so the question is if you can heat
>> up the soc from say 80°C (first trip point) to over 110°C in less than
>> that period (330ms currently).
>>
>> I say it shouldn't be a problem, if that small thing is drawing say 2W
>> at max load. It will burn or trigger a second trip point before the
>> first one has a chance to trigger and the kernel will shut down. I
>> remember tkaiser saying that he has to run that board at 240MHz max. But
>> perhaps I'm misremembering.
>>
>> I'm just speculating.
> 
> Yes, but that's just poor thermal design. What I was saying is that
> even if we really need to throttle the SoC to 240 MHz on that board
> because it heats too much, the couple of the frequency and the voltage
> will likely be the same across all boards. It's just the amount of
> time we'll spend using it that will differ.
> 
> But that's just my understanding, I might be speaking non-sense :)
> 
> Maxime
> 

You're probably right. Operating points should be part of h3.dtsi, and
if some board is particularly bad, and can't handle being above certain
frequency safely, due to thermal design issues, we can override
operating points in its dts file.

regards,
  Ondrej

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#1434463 — Re: [linux-sunxi] Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi

Hello,

On 29 June 2016 at 23:11, Ondřej Jirman <megous@megous.com> wrote:
> On 29.6.2016 22:45, Maxime Ripard wrote:
>> Hi,
>>
>> On Sat, Jun 25, 2016 at 04:50:24PM +0200, Ondřej Jirman wrote:
>>> On 25.6.2016 09:02, Maxime Ripard wrote:
>>>> On Sat, Jun 25, 2016 at 09:02:48AM +0800, Chen-Yu Tsai wrote:
>>>>> On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <megous@megous.com> wrote:
>>>>>> Hello,
>>>>>>
>>>>>> comments below.
>>>>>>
>>>>>> On 24.6.2016 05:48, Chen-Yu Tsai wrote:
>>>>>>> On Fri, Jun 24, 2016 at 3:20 AM,  <megous@megous.com> wrote:
>>>>>>>> From: Ondrej Jirman <megous@megous.com>
>>>>>>>>
>>>>>>>> Add label to the first cpu so that it can be referenced
>>>>>>>> from derived dts files.
>>>>>>>>
>>>>>>>> Signed-off-by: Ondrej Jirman <megous@megous.com>
>>>>>>>> ---
>>>>>>>>  arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
>>>>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>>>>> index 9938972..82faefc 100644
>>>>>>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>>>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>>>>>>>> @@ -52,7 +52,7 @@
>>>>>>>>                 #address-cells = <1>;
>>>>>>>>                 #size-cells = <0>;
>>>>>>>>
>>>>>>>> -               cpu@0 {
>>>>>>>> +               cpu0: cpu@0 {
>>>>>>>>                         compatible = "arm,cortex-a7";
>>>>>>>>                         device_type = "cpu";
>>>>>>>>                         reg = <0>;
>>>>>>>
>>>>>>> Can you also set the cpu clock here? It is part of the SoC
>>>>>>> and does not belong in the board DTS files.
>>>>>>
>>>>>> Do you mean operating-points, or something else? Different SBCs will
>>>>>> probably require different combinations of operating points just for
>>>>>> safety's sake, because they have different regulators and [some have
>>>>>> botched] thermal designs, so it might make sense to customize it for
>>>>>> differnt boards, and I don't feel adventurous enough setting it for all
>>>>>> H3 boards out there.
>>>>>
>>>>> I meant clocks = <...> and clock-latency = <...>.
>>>>>
>>>>> These 2 are part of the SoC.
>>>>>
>>>>> The OPP can stay in the board files. It's a pity there's no standard
>>>>> OPP table for H3 though. :(
>>>>
>>>> This has never been the case, and we always had some deviation in the
>>>> FEX files for all the SoCs.
>>>>
>>>> If we could come up with standard OPPs that work for every one,
>>>> there's no reason it can't happen here.
>>>>
>>>> I don't really see why the thermal design should change anything. If a
>>>> boards heats faster, it will throttle down to a lower OPP faster, but
>>>> those OPPs are not going to change.
>>>
>>> I've no way to test, but I've been told some Sinovoip boards are really
>>> bad in this regard (SoC is not even well thermally connected to the
>>> PCB/PCB not having copper layer to spread the heat). Thermal sensor
>>> readings happen at fixed intervals, so the question is if you can heat
>>> up the soc from say 80°C (first trip point) to over 110°C in less than
>>> that period (330ms currently).
>>>
>>> I say it shouldn't be a problem, if that small thing is drawing say 2W
>>> at max load. It will burn or trigger a second trip point before the
>>> first one has a chance to trigger and the kernel will shut down. I
>>> remember tkaiser saying that he has to run that board at 240MHz max. But
>>> perhaps I'm misremembering.
>>>
>>> I'm just speculating.
>>
>> Yes, but that's just poor thermal design. What I was saying is that
>> even if we really need to throttle the SoC to 240 MHz on that board
>> because it heats too much, the couple of the frequency and the voltage
>> will likely be the same across all boards. It's just the amount of
>> time we'll spend using it that will differ.
>>
>> But that's just my understanding, I might be speaking non-sense :)
>>
>> Maxime
>>
>
> You're probably right. Operating points should be part of h3.dtsi, and
> if some board is particularly bad, and can't handle being above certain
> frequency safely, due to thermal design issues, we can override
> operating points in its dts file.
>

Can you override them?

AFAIK you cannot replace a property set in SoC file in a board file.
If you can keep the operating point list and just add option which
selects acceptable subset for the board that should work. On some
boards this subset would be determined by regulator voltage
constraints but not sure how you would select the subset for the
boards with thermal problems.

Thanks

Michal

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#1434836 — Re: [linux-sunxi] Re: [PATCH 06/14] ARM: dts: sun8i: Add cpu0 label to sun8i-h3.dtsi

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On Thu, Jun 30, 2016 at 01:04:40PM +0200, Michal Suchanek wrote:
> > You're probably right. Operating points should be part of h3.dtsi, and
> > if some board is particularly bad, and can't handle being above certain
> > frequency safely, due to thermal design issues, we can override
> > operating points in its dts file.
> >
> 
> Can you override them?
> 
> AFAIK you cannot replace a property set in SoC file in a board file.

You totally can, we have litterally dozens of examples of that already.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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