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Re: [PATCH v2 00/13] sched: Clean-ups and asymmetric cpu capacity support

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  Re: [PATCH v2 00/13] sched: Clean-ups and asymmetric cpu capacity support Koan-Sin Tan <koansin.tan@gmail.com> - 2016-06-28 12:30 +0200
    Re: [PATCH v2 00/13] sched: Clean-ups and asymmetric cpu capacity  support Morten Rasmussen <morten.rasmussen@arm.com> - 2016-06-30 10:00 +0200

#1432721 — Re: [PATCH v2 00/13] sched: Clean-ups and asymmetric cpu capacity support

Hi,

I tested these patches with patches from your preview branch [1] and some
platform specific patches on MediaTek MT8173 EVB (integrated branch at [2])

> Test 0:
> 	for i in `seq 1 10`; \
> 	       do sysbench --test=cpu --max-time=3 --num-threads=1 run; \
> 	       done \
> 	| awk '{if ($4=="events:") {print $5; sum +=$5; runs +=1}} \
> 	       END {print "Average events: " sum/runs}'
> Target: ARM TC2 (2xA15+3xA7)
> 
> 	(Higher is better)
> tip:	Average events: 146.9
> patch:	Average events: 217.9

Target: MediaTek MT8173 EVB (2xA53+2xA72)

w/o capacity patches:
	274.7 (actually, it varies a lot between 194 and 329
w/ capacity patches:
	328.7

> Test 1:
> 	perf stat --null --repeat 10 -- \
> 	perf bench sched messaging -g 50 -l 5000
> 
> Target: Intel IVB-EP (2*10*2)
> 
> tip:    4.861970420 seconds time elapsed ( +-  1.39% )
> patch:  4.886204224 seconds time elapsed ( +-  0.75% )
> 
> Target: ARM TC2 A7-only (3xA7) (-l 1000)
> 
> tip:    61.485682596 seconds time elapsed ( +-  0.07% )
> patch:  62.667950130 seconds time elapsed ( +-  0.36% )
> 

Target: MediaTek MT8173 EVB A53-only (2xA7) (-l 1000)

w/o capacity patches:
	72.663181227 seconds time elapsed ( +-  1.62% )
	71.502263666 seconds time elapsed ( +-  0.45% ) 
	73.707466212 seconds time elapsed ( +-  0.99% )
        73.623523997 seconds time elapsed ( +-  1.85% )
     	74.150137066 seconds time elapsed ( +-  1.41% )

w/ capacity patches:
	70.360055056 seconds time elapsed ( +-  1.58% ) 
	69.884793481 seconds time elapsed ( +-  0.78% )
	73.395917166 seconds time elapsed ( +-  1.86% )
	70.082440427 seconds time elapsed ( +-  1.66% )
	69.365401758 seconds time elapsed ( +-  0.80% )

Tested-by: Koan-Sin Tan <freedom.tan@mediatek.com>

[1] git://linux-arm.org/linux-power.git capacity_awareness_v2_arm64_v1
[2] https://git.linaro.org/people/freedom.tan/linux-8173.git v4.7-rc5-mt8173-capacity

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#1434316 — Re: [PATCH v2 00/13] sched: Clean-ups and asymmetric cpu capacity support

On Tue, Jun 28, 2016 at 06:20:27PM +0800, Koan-Sin Tan wrote:
> Hi,
> 
> I tested these patches with patches from your preview branch [1] and some
> platform specific patches on MediaTek MT8173 EVB (integrated branch at [2])
> 
> > Test 0:
> > 	for i in `seq 1 10`; \
> > 	       do sysbench --test=cpu --max-time=3 --num-threads=1 run; \
> > 	       done \
> > 	| awk '{if ($4=="events:") {print $5; sum +=$5; runs +=1}} \
> > 	       END {print "Average events: " sum/runs}'
> > Target: ARM TC2 (2xA15+3xA7)
> > 
> > 	(Higher is better)
> > tip:	Average events: 146.9
> > patch:	Average events: 217.9
> 
> Target: MediaTek MT8173 EVB (2xA53+2xA72)
> 
> w/o capacity patches:
> 	274.7 (actually, it varies a lot between 194 and 329

The variation you mention is consistent with our observations on both
TC2 and Juno. Most times you get either big or little performance, and
occasionally a number in between.

> w/ capacity patches:
> 	328.7
> 
> > Test 1:
> > 	perf stat --null --repeat 10 -- \
> > 	perf bench sched messaging -g 50 -l 5000
> > 
> > Target: Intel IVB-EP (2*10*2)
> > 
> > tip:    4.861970420 seconds time elapsed ( +-  1.39% )
> > patch:  4.886204224 seconds time elapsed ( +-  0.75% )
> > 
> > Target: ARM TC2 A7-only (3xA7) (-l 1000)
> > 
> > tip:    61.485682596 seconds time elapsed ( +-  0.07% )
> > patch:  62.667950130 seconds time elapsed ( +-  0.36% )
> > 
> 
> Target: MediaTek MT8173 EVB A53-only (2xA7) (-l 1000)
> 
> w/o capacity patches:
> 	72.663181227 seconds time elapsed ( +-  1.62% )
> 	71.502263666 seconds time elapsed ( +-  0.45% ) 
> 	73.707466212 seconds time elapsed ( +-  0.99% )
>         73.623523997 seconds time elapsed ( +-  1.85% )
>      	74.150137066 seconds time elapsed ( +-  1.41% )
> 
> w/ capacity patches:
> 	70.360055056 seconds time elapsed ( +-  1.58% ) 
> 	69.884793481 seconds time elapsed ( +-  0.78% )
> 	73.395917166 seconds time elapsed ( +-  1.86% )
> 	70.082440427 seconds time elapsed ( +-  1.66% )
> 	69.365401758 seconds time elapsed ( +-  0.80% )
> 
> Tested-by: Koan-Sin Tan <freedom.tan@mediatek.com>

Thanks for testing.

Morten

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