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Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

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  Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband  bridge support driver for Intel SOC's Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-06-13 16:00 +0200
    Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge  support driver for Intel SOC's Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-06-13 16:30 +0200
      Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband  bridge support driver for Intel SOC's Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-06-13 17:20 +0200
        Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge  support driver for Intel SOC's Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-06-13 18:00 +0200
          RE: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband  bridge support driver for Intel SOC's "Tan, Jui Nee" <jui.nee.tan@intel.com> - 2016-06-21 07:10 +0200
            Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge  support driver for Intel SOC's Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-06-21 09:50 +0200

#1420873 — Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

On Thu, 2016-06-09 at 17:05 +0300, Mika Westerberg wrote:
> On Tue, Jun 07, 2016 at 02:55:52PM +0800, Tan Jui Nee wrote:
> > From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > 
> > There is already one and at least one more user coming which
> > require an access to Primary to Sideband bridge (P2SB) in order
> > to get IO or MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> > 
> > Signed-off-by: Yong, Jonathan <jonathan.yong@intel.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > ---
> >  arch/x86/Kconfig                 | 14 ++++++
> >  arch/x86/include/asm/p2sb.h      | 27 +++++++++++
> >  arch/x86/platform/intel/Makefile |  1 +
> >  arch/x86/platform/intel/p2sb.c   | 99
> > ++++++++++++++++++++++++++++++++++++++++
> >  4 files changed, 141 insertions(+)
> >  create mode 100644 arch/x86/include/asm/p2sb.h
> >  create mode 100644 arch/x86/platform/intel/p2sb.c
> > 
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > index 2dc18605..589045e 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -606,6 +606,20 @@ config IOSF_MBI_DEBUG
> >  
> >  	  If you don't require the option or are in doubt, say N.
> >  
> > +config X86_INTEL_NON_ACPI
> > +	bool "Enable support non-ACPI Intel platforms"
> > +	select PINCTRL
> > +	---help---
> > +	  Select this option to enables MMIO BAR access over the
> > P2SB for
> > +	  non-ACPI Intel SoC platforms. This driver uses the P2SB
> > hide/unhide
> > +	  mechanism cooperatively to pass the PCI BAR address to
> > the platform
> > +	  driver, currently GPIO on the following SoC products.
> > +	   - Apollo Lake
> 
> Why do we need Kconfig option for this?

In one of previous review I was wondering how we could not to build this
at all. I don't like this option either.

> 
> I think better is to make P2SB available on CPUs which have one, and
> that can be detected runtime. If P2SB is not available then p2sb_bar()
> returns -ENODEV.

Would work to me, though still the same question: is it possible to
avoid building it on even most of Intel platforms, since there, I
assume, will be not many users of the module?

-- 

Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

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#1420928 — Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

On Mon, Jun 13, 2016 at 04:54:31PM +0300, Andy Shevchenko wrote:
> Would work to me, though still the same question: is it possible to
> avoid building it on even most of Intel platforms, since there, I
> assume, will be not many users of the module?

Well, even if you make it configurable via Kconfig, I guess distros will
have to enable it in order to support as wide range of CPUs as possible
in a single binary.

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#1420980

On Mon, 2016-06-13 at 17:25 +0300, Mika Westerberg wrote:
> On Mon, Jun 13, 2016 at 04:54:31PM +0300, Andy Shevchenko wrote:
> > Would work to me, though still the same question: is it possible to
> > avoid building it on even most of Intel platforms, since there, I
> > assume, will be not many users of the module?
> 
> Well, even if you make it configurable via Kconfig, I guess distros
> will
> have to enable it in order to support as wide range of CPUs as
> possible
> in a single binary.

Good point.

Then perhaps the following we can do:
 - add a static boolean flag
 - add __init function where we check either PCI root bridge ID or CPU
ID (I don't know which one is better, I suppose second one, though it
will require an update of arch/x86/include/asm/intel-family.h)
 - add a check into the function.

What do you think?

-- 

Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

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#1421024 — Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

On Mon, Jun 13, 2016 at 06:19:12PM +0300, Andy Shevchenko wrote:
> On Mon, 2016-06-13 at 17:25 +0300, Mika Westerberg wrote:
> > On Mon, Jun 13, 2016 at 04:54:31PM +0300, Andy Shevchenko wrote:
> > > Would work to me, though still the same question: is it possible to
> > > avoid building it on even most of Intel platforms, since there, I
> > > assume, will be not many users of the module?
> > 
> > Well, even if you make it configurable via Kconfig, I guess distros
> > will
> > have to enable it in order to support as wide range of CPUs as
> > possible
> > in a single binary.
> 
> Good point.
> 
> Then perhaps the following we can do:
>  - add a static boolean flag
>  - add __init function where we check either PCI root bridge ID or CPU
> ID (I don't know which one is better, I suppose second one, though it
> will require an update of arch/x86/include/asm/intel-family.h)
>  - add a check into the function.
> 
> What do you think?

Maybe, or make it modular and use MODULE_DEVICE_TABLE(x86cpu, ...) to
match the corresponding CPUs.

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#1427304

> -----Original Message-----
> From: Mika Westerberg [mailto:mika.westerberg@linux.intel.com]
> Sent: Monday, June 13, 2016 11:59 PM
> To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Tan, Jui Nee <jui.nee.tan@intel.com>; heikki.krogerus@linux.intel.com;
> tglx@linutronix.de; mingo@redhat.com; hpa@zytor.com; x86@kernel.org;
> ptyser@xes-inc.com; lee.jones@linaro.org; linux-gpio@vger.kernel.org;
> linux-kernel@vger.kernel.org; Yong, Jonathan <jonathan.yong@intel.com>;
> Yu, Ong Hock <ong.hock.yu@intel.com>; Voon, Weifeng
> <weifeng.voon@intel.com>; Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.mohamad@intel.com>
> Subject: Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband
> bridge support driver for Intel SOC's
> 
> On Mon, Jun 13, 2016 at 06:19:12PM +0300, Andy Shevchenko wrote:
> > On Mon, 2016-06-13 at 17:25 +0300, Mika Westerberg wrote:
> > > On Mon, Jun 13, 2016 at 04:54:31PM +0300, Andy Shevchenko wrote:
> > > > Would work to me, though still the same question: is it possible
> > > > to avoid building it on even most of Intel platforms, since there,
> > > > I assume, will be not many users of the module?
> > >
> > > Well, even if you make it configurable via Kconfig, I guess distros
> > > will have to enable it in order to support as wide range of CPUs as
> > > possible in a single binary.
> >
> > Good point.
> >
> > Then perhaps the following we can do:
> >  - add a static boolean flag
> >  - add __init function where we check either PCI root bridge ID or CPU
> > ID (I don't know which one is better, I suppose second one, though it
> > will require an update of arch/x86/include/asm/intel-family.h)
> >  - add a check into the function.
> >
> > What do you think?
> 
> Maybe, or make it modular and use MODULE_DEVICE_TABLE(x86cpu, ...) to
> match the corresponding CPUs.
We need CONFIG_X86_INTEL_NON_ACPI Kconfig option to select CONFIG_PINCTRL.
This is to solve kbuidbot complaint about kernel configuration, i.e.
CONFIG_PINCTRL=n. Appreciate if you could advise something on this.

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#1427422 — Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

On Tue, Jun 21, 2016 at 05:03:20AM +0000, Tan, Jui Nee wrote:
> > Maybe, or make it modular and use MODULE_DEVICE_TABLE(x86cpu, ...) to
> > match the corresponding CPUs.
>
> We need CONFIG_X86_INTEL_NON_ACPI Kconfig option to select CONFIG_PINCTRL.
> This is to solve kbuidbot complaint about kernel configuration, i.e.
> CONFIG_PINCTRL=n. Appreciate if you could advise something on this.

Good point.

Then I guess you might add similar Kconfig option but can you call it
something else than CONFIG_X86_INTEL_NON_ACPI. Perhaps something that
relates to the actual product so distro people can then decide whether
they want to support it or not. Along the lines of CONFIG_X86_INTEL_CE
and so on.

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