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[PATCH V2] coresight: document binding acronyms

Started byMathieu Poirier <mathieu.poirier@linaro.org>
First post2016-06-22 17:10 +0200
Last post2016-06-22 19:20 +0200
Articles 3 — 3 participants

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  [PATCH V2] coresight: document binding acronyms Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-06-22 17:10 +0200
    Re: [PATCH V2] coresight: document binding acronyms Sudeep Holla <sudeep.holla@arm.com> - 2016-06-22 18:50 +0200
    Re: [PATCH V2] coresight: document binding acronyms Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2016-06-22 19:20 +0200

#1428881 — [PATCH V2] coresight: document binding acronyms

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2016-06-22 17:10 +0200
Subject[PATCH V2] coresight: document binding acronyms
Message-ID<rMRWV-53e-17@gated-at.bofh.it>
It can be hard for people not familiar with the CoreSight IP blocks
to make sense of the acronyms found in the current bindings.  As such
this patch expands each acronym in the hope of providing a better
description of the IP block they represent.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 .../devicetree/bindings/arm/coresight.txt          | 35 +++++++++++++++++-----
 1 file changed, 27 insertions(+), 8 deletions(-)

Changes since V1:
   - Expanded ETB, ETF and ETR acronyms.
   - Added note about using the same binding
     for all 3 modes (ETB, ETF, ETR).

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 93147c0c8a0e..fcbae6a5e6c1 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -12,14 +12,33 @@ its hardware characteristcs.
 
 	* compatible: These have to be supplemented with "arm,primecell" as
 	  drivers are using the AMBA bus interface.  Possible values include:
-		- "arm,coresight-etb10", "arm,primecell";
-		- "arm,coresight-tpiu", "arm,primecell";
-		- "arm,coresight-tmc", "arm,primecell";
-		- "arm,coresight-funnel", "arm,primecell";
-		- "arm,coresight-etm3x", "arm,primecell";
-		- "arm,coresight-etm4x", "arm,primecell";
-		- "qcom,coresight-replicator1x", "arm,primecell";
-		- "arm,coresight-stm", "arm,primecell"; [1]
+		- Embedded Trace Buffer (version 1.0):
+			"arm,coresight-etb10", "arm,primecell";
+
+		- Trace Port Interface Unit:
+			"arm,coresight-tpiu", "arm,primecell";
+
+		- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
+		  Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
+		  configuration.  The configuration mode (ETB, ETF, ETR) is
+		  discovered at boot time when the device is probed.
+			"arm,coresight-tmc", "arm,primecell";
+
+		- Trace Funnel:
+			"arm,coresight-funnel", "arm,primecell";
+
+		- Embedded Trace Macrocell (version 3.x) and
+					Program Flow Trace Macrocell:
+			"arm,coresight-etm3x", "arm,primecell";
+
+		- Embedded Trace Macrocell (version 4.x):
+			"arm,coresight-etm4x", "arm,primecell";
+
+		- Qualcomm Configurable Replicator (version 1.x):
+			"qcom,coresight-replicator1x", "arm,primecell";
+
+		- System Trace Macrocell:
+			"arm,coresight-stm", "arm,primecell"; [1]
 
 	* reg: physical base address and length of the register
 	  set(s) of the component.
-- 
2.7.4

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#1428973

FromSudeep Holla <sudeep.holla@arm.com>
Date2016-06-22 18:50 +0200
Message-ID<rMTvJ-5UI-57@gated-at.bofh.it>
In reply to#1428881

On 22/06/16 16:01, Mathieu Poirier wrote:
> It can be hard for people not familiar with the CoreSight IP blocks
> to make sense of the acronyms found in the current bindings.  As such
> this patch expands each acronym in the hope of providing a better
> description of the IP block they represent.
>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
>   .../devicetree/bindings/arm/coresight.txt          | 35 +++++++++++++++++-----
>   1 file changed, 27 insertions(+), 8 deletions(-)
>
> Changes since V1:
>     - Expanded ETB, ETF and ETR acronyms.
>     - Added note about using the same binding
>       for all 3 modes (ETB, ETF, ETR).
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 93147c0c8a0e..fcbae6a5e6c1 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -12,14 +12,33 @@ its hardware characteristcs.
>
>   	* compatible: These have to be supplemented with "arm,primecell" as
>   	  drivers are using the AMBA bus interface.  Possible values include:
> -		- "arm,coresight-etb10", "arm,primecell";
> -		- "arm,coresight-tpiu", "arm,primecell";
> -		- "arm,coresight-tmc", "arm,primecell";
> -		- "arm,coresight-funnel", "arm,primecell";
> -		- "arm,coresight-etm3x", "arm,primecell";
> -		- "arm,coresight-etm4x", "arm,primecell";
> -		- "qcom,coresight-replicator1x", "arm,primecell";
> -		- "arm,coresight-stm", "arm,primecell"; [1]
> +		- Embedded Trace Buffer (version 1.0):
> +			"arm,coresight-etb10", "arm,primecell";
> +
> +		- Trace Port Interface Unit:
> +			"arm,coresight-tpiu", "arm,primecell";
> +
> +		- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
> +		  Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
> +		  configuration.  The configuration mode (ETB, ETF, ETR) is
> +		  discovered at boot time when the device is probed.
> +			"arm,coresight-tmc", "arm,primecell";
> +
> +		- Trace Funnel:
> +			"arm,coresight-funnel", "arm,primecell";
> +
> +		- Embedded Trace Macrocell (version 3.x) and
> +					Program Flow Trace Macrocell:
> +			"arm,coresight-etm3x", "arm,primecell";
> +
> +		- Embedded Trace Macrocell (version 4.x):
> +			"arm,coresight-etm4x", "arm,primecell";
> +
> +		- Qualcomm Configurable Replicator (version 1.x):
> +			"qcom,coresight-replicator1x", "arm,primecell";
> +
> +		- System Trace Macrocell:
> +			"arm,coresight-stm", "arm,primecell"; [1]


Looks good to me.

Acked-by: Sudeep Holla <sudeep.holla@arm.com>

-- 
Regards,
Sudeep

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#1429014

FromSuzuki K Poulose <Suzuki.Poulose@arm.com>
Date2016-06-22 19:20 +0200
Message-ID<rMTYJ-6lC-7@gated-at.bofh.it>
In reply to#1428881
On 22/06/16 16:01, Mathieu Poirier wrote:
> It can be hard for people not familiar with the CoreSight IP blocks
> to make sense of the acronyms found in the current bindings.  As such
> this patch expands each acronym in the hope of providing a better
> description of the IP block they represent.
>


Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Suzuki

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