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[PATCH 0/5] pwm: Fixes and support for Tegra186

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  [PATCH 0/5] pwm: Fixes and support for Tegra186 Laxman Dewangan <ldewangan@nvidia.com> - 2016-06-22 14:10 +0200
    [PATCH 3/5] pwm: tegra: fix overflow when calculating duty cycle Laxman Dewangan <ldewangan@nvidia.com> - 2016-06-22 14:10 +0200
    [PATCH 2/5] pwm: tegra: Allow 100% duty cycle Laxman Dewangan <ldewangan@nvidia.com> - 2016-06-22 14:10 +0200
    [PATCH 4/5] pwm: tegra: Add DT node compatible for Tegra186 Laxman Dewangan <ldewangan@nvidia.com> - 2016-06-22 14:10 +0200
      Re: [PATCH 4/5] pwm: tegra: Add DT node compatible for Tegra186 Thierry Reding <thierry.reding@gmail.com> - 2016-06-22 14:50 +0200
    [PATCH 5/5] pwm: tegra: Add support for Tegra186 Laxman Dewangan <ldewangan@nvidia.com> - 2016-06-22 14:10 +0200

#1428727 — [PATCH 0/5] pwm: Fixes and support for Tegra186

Have fixes for 100% duty cycle, avoid computation loss for duty
period calculation and add support the Tegra186.

Hyong Bin Kim (1):
  pwm: tegra: fix overflow when calculating duty cycle

Laxman Dewangan (2):
  pwm: tegra: Add DT node compatible for Tegra186
  pwm: tegra: Add support for Tegra186

Rohith Seelaboyina (1):
  pwm: tegra: Add support for reset control

Victor(Weiguo) Pan (1):
  pwm: tegra: Allow 100% duty cycle

 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 10 +++--
 drivers/pwm/pwm-tegra.c                            | 46 ++++++++++++++++++----
 2 files changed, 45 insertions(+), 11 deletions(-)

-- 
2.1.4

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#1428730 — [PATCH 3/5] pwm: tegra: fix overflow when calculating duty cycle

From: Hyong Bin Kim <hyongbink@nvidia.com>

duty_ns * (1 << PWM_DUTY_WIDTH) could overflow in integer calcualtion
when PWM rate is low. Hence do all calculation on unsigned long long
to avoid overflow.

Signed-off-by: Hyong Bin Kim <hyongbink@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 drivers/pwm/pwm-tegra.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 575ca8e..49cefd5 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -69,7 +69,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 			    int duty_ns, int period_ns)
 {
 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
-	unsigned long long c;
+	unsigned long long c = duty_ns;
 	unsigned long rate, hz;
 	u32 val = 0;
 	int err;
@@ -79,7 +79,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
 	 * nearest integer during division.
 	 */
-	c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
+	c *= (1 << PWM_DUTY_WIDTH);
+	c += period_ns / 2;
 	do_div(c, period_ns);
 
 	val = (u32)c << PWM_DUTY_SHIFT;
-- 
2.1.4

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#1428733 — [PATCH 2/5] pwm: tegra: Allow 100% duty cycle

From: "Victor(Weiguo) Pan" <wpan@nvidia.com>

To get 100% duty cycle (always high), pulse width needs to be
set to 256.

Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 drivers/pwm/pwm-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 71b9c4d..575ca8e 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -79,7 +79,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
 	 * nearest integer during division.
 	 */
-	c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
+	c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
 	do_div(c, period_ns);
 
 	val = (u32)c << PWM_DUTY_SHIFT;
-- 
2.1.4

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#1428735 — [PATCH 4/5] pwm: tegra: Add DT node compatible for Tegra186

Tegra186 has 8 different PWM controller and each controller has only
one output. Earlier generation SoCs have the 4 PWM output per controller.

Add DT node compatible for Tegra186.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index c52f03b..2851b2d 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -1,10 +1,12 @@
 Tegra SoC PWFM controller
 
 Required properties:
-- compatible: For Tegra20, must contain "nvidia,tegra20-pwm".  For Tegra30,
-  must contain "nvidia,tegra30-pwm".  Otherwise, must contain
-  "nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114,
-  tegra124, tegra132, or tegra210.
+- compatible: For Tegra20, must contain "nvidia,tegra20-pwm".
+	      For Tegra30, must contain "nvidia,tegra30-pwm".
+	      For Tegra114, Tegra124, Tegra132, Tegra210 must contain
+	      "nvidia,<chip>-pwm", plus one of the above, where <chip> is
+	      tegra114, tegra124, tegra132, or tegra210.
+	      For Tegra186, must contain "nvidia,tegra186-pwm".
 - reg: physical base address and length of the controller's registers
 - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
   the cells format.
-- 
2.1.4

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#1428767 — Re: [PATCH 4/5] pwm: tegra: Add DT node compatible for Tegra186

[Multipart message — attachments visible in raw view] — view raw

On Wed, Jun 22, 2016 at 05:17:22PM +0530, Laxman Dewangan wrote:
> Tegra186 has 8 different PWM controller and each controller has only
> one output. Earlier generation SoCs have the 4 PWM output per controller.
> 
> Add DT node compatible for Tegra186.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
>  Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> index c52f03b..2851b2d 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -1,10 +1,12 @@
>  Tegra SoC PWFM controller
>  
>  Required properties:
> -- compatible: For Tegra20, must contain "nvidia,tegra20-pwm".  For Tegra30,
> -  must contain "nvidia,tegra30-pwm".  Otherwise, must contain
> -  "nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114,
> -  tegra124, tegra132, or tegra210.
> +- compatible: For Tegra20, must contain "nvidia,tegra20-pwm".
> +	      For Tegra30, must contain "nvidia,tegra30-pwm".
> +	      For Tegra114, Tegra124, Tegra132, Tegra210 must contain
> +	      "nvidia,<chip>-pwm", plus one of the above, where <chip> is
> +	      tegra114, tegra124, tegra132, or tegra210.
> +	      For Tegra186, must contain "nvidia,tegra186-pwm".

Rob, I recall discussing this with you a couple of weeks ago, but fail
to remember the outcome and can't find a link to the discussion either.
Wasn't there a new standard way of documenting this kind of compatible
string list?

Or did you say it didn't matter much until we moved to a YAML-based
description?

Thierry

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#1428737 — [PATCH 5/5] pwm: tegra: Add support for Tegra186

Tegra186 has PWM controller with only one output instead of
4 output in earlier generation SoCs.

Add support for Tegra186 and find the number of PWM output
based on driver data.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 drivers/pwm/pwm-tegra.c | 31 ++++++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 49cefd5..5547e7d 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -26,6 +26,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/pwm.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
@@ -37,7 +38,9 @@
 #define PWM_SCALE_WIDTH	13
 #define PWM_SCALE_SHIFT	0
 
-#define NUM_PWM 4
+struct tegra_pwm_hwdata {
+	int num_pwm;
+};
 
 struct tegra_pwm_chip {
 	struct pwm_chip		chip;
@@ -47,6 +50,7 @@ struct tegra_pwm_chip {
 	struct reset_control	*rstc;
 
 	void __iomem		*mmio_base;
+	const struct tegra_pwm_hwdata	*hw;
 };
 
 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
@@ -172,9 +176,16 @@ static const struct pwm_ops tegra_pwm_ops = {
 static int tegra_pwm_probe(struct platform_device *pdev)
 {
 	struct tegra_pwm_chip *pwm;
+	const struct tegra_pwm_hwdata *hwdata;
 	struct resource *r;
 	int ret;
 
+	hwdata = of_device_get_match_data(&pdev->dev);
+	if (!hwdata) {
+		dev_err(&pdev->dev, "Tegra PWM HW data not found\n");
+		return -ENODEV;
+	}
+
 	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 	if (!pwm)
 		return -ENOMEM;
@@ -200,10 +211,11 @@ static int tegra_pwm_probe(struct platform_device *pdev)
 	}
 	reset_control_reset(pwm->rstc);
 
+	pwm->hw = hwdata;
 	pwm->chip.dev = &pdev->dev;
 	pwm->chip.ops = &tegra_pwm_ops;
 	pwm->chip.base = -1;
-	pwm->chip.npwm = NUM_PWM;
+	pwm->chip.npwm = pwm->hw->num_pwm;
 
 	ret = pwmchip_add(&pwm->chip);
 	if (ret < 0) {
@@ -222,7 +234,7 @@ static int tegra_pwm_remove(struct platform_device *pdev)
 	if (WARN_ON(!pc))
 		return -ENODEV;
 
-	for (i = 0; i < NUM_PWM; i++) {
+	for (i = 0; i < pc->hw->num_pwm; i++) {
 		struct pwm_device *pwm = &pc->chip.pwms[i];
 
 		if (!pwm_is_enabled(pwm))
@@ -237,9 +249,18 @@ static int tegra_pwm_remove(struct platform_device *pdev)
 	return pwmchip_remove(&pc->chip);
 }
 
+static const struct tegra_pwm_hwdata tegra20_pwm_hw = {
+	.num_pwm = 4,
+};
+
+static const struct tegra_pwm_hwdata tegra186_pwm_hw = {
+	.num_pwm = 1,
+};
+
 static const struct of_device_id tegra_pwm_of_match[] = {
-	{ .compatible = "nvidia,tegra20-pwm" },
-	{ .compatible = "nvidia,tegra30-pwm" },
+	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_hw },
+	{ .compatible = "nvidia,tegra30-pwm", .data = &tegra20_pwm_hw },
+	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_hw, },
 	{ }
 };
 
-- 
2.1.4

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