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Re: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

Started byHeiko Stübner <heiko@sntech.de>
First post2016-06-17 01:20 +0200
Last post2016-06-21 11:20 +0200
Articles 4 — 2 participants

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  Re: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation Heiko Stübner <heiko@sntech.de> - 2016-06-17 01:20 +0200
    Re: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation William Wu <william.wu@rock-chips.com> - 2016-06-17 11:20 +0200
      Re: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation Heiko Stübner <heiko@sntech.de> - 2016-06-20 16:50 +0200
        Re: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation William Wu <william.wu@rock-chips.com> - 2016-06-21 11:20 +0200

#1424528 — Re: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

FromHeiko Stübner <heiko@sntech.de>
Date2016-06-17 01:20 +0200
SubjectRe: [PATCH v4 5/5] usb: dwc3: rockchip: add devicetree bindings documentation
Message-ID<rKOJP-6hN-1@gated-at.bofh.it>
Hi William,

Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
> This patch adds the devicetree documentation required for Rockchip
> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
> 
> It supports DRD mode, and could operate in device mode (SS, HS, FS)
> and host mode (SS, HS, FS, LS).
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>

devicetree binding documentation patches should include the devicetree 
maintainers (scripts/get_maintainer.pl)

> ---
> Changes in v4:
> - modify commit log, and add phy documentation location (Sergei)
> 
> Changes in v3:
> - add dwc3 address (balbi)
> 
> Changes in v2:
> - add rockchip,dwc3.txt to Documentation/devicetree/bindings/ (balbi, 
Brian)
> 
>  .../devicetree/bindings/usb/rockchip,dwc3.txt      | 46
> ++++++++++++++++++++++ 1 file changed, 46 insertions(+)
>  create mode 100644 
Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> 
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt new file mode
> 100644
> index 0000000..0edf013
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> @@ -0,0 +1,46 @@
> +Rockchip SuperSpeed DWC3 USB SoC controller
> +
> +Required properties:
> +- compatible:	should contain "rockchip,dwc3"

are you sure this will work for all future socs in the same way? I guess 
doing this as rockchip,rk3399-dwc3 might make our lifes easier down the road 
:-) [both the xilinx and st dwc3 bindings do already that]

> +- clocks:		A list of phandle + clock-specifier pairs for the
> +				clocks listed in clock-names
> +- clock-names:	Should contain the following:
> +  "clk_usb3otg0_ref"	Controller reference clk
> +  "clk_usb3otg0_suspend"Controller suspend clk, can use 24 MHz or 32 KHz
> +  "aclk_usb3"		Master/Core clock, have to be >= 62.5 MHz for SS 
operation

clock names should always be in the scope of the device block (named after 
what it supplies). And looking at the dwc3-xilinx.txt binding, I'd suggest 
getting inspiration from their clock names (bus_clk, ref_clk, suspend_clk or 
so)

> +Optional clocks:
> +  "aclk_usb3otg0"	Aclk for specific usb controller clock.
> +  "aclk_usb3_rksoc_axi_perf"  USB AXI perf clock.  Not present on all
> platforms. 

The clock names looks pretty strange. What are they for? Especially as 
nothing seems to use them right now.


> +  "aclk_usb3_grf"	USB grf clock.  Not present on all platforms.

for my own education, which part of the GRF does this clock supply?


> +
> +Required child node:
> +A child node must exist to represent the core DWC3 IP block. The name of
> +the node is not important. The content of the node is defined in dwc3.txt.
> +
> +Phy documentation is provided in the following places:
> +Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
> +
> +Example device nodes:
> +
> +	usbdrd3_0: usb@fe800000 {
> +		compatible = "rockchip,dwc3";
> +		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> +			 <&cru ACLK_USB3>, <&cru ACLK_USB3OTG0>,
> +			 <&cru ACLK_USB3_RKSOC_AXI_PERF>, <&cru ACLK_USB3_GRF>;
> +		clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
> +			      "aclk_usb3", "aclk_usb3otg0",
> +			      "aclk_usb3_rksoc_axi_perf", "aclk_usb3_grf";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		status = "disabled";
> +		usbdrd_dwc3_0: dwc3@fe800000 {
> +			compatible = "snps,dwc3";
> +			reg = <0x0 0xfe800000 0x0 0x100000>;
> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			dr_mode = "otg";
> +			status = "disabled";
> +		};
> +	};

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#1424840

FromWilliam Wu <william.wu@rock-chips.com>
Date2016-06-17 11:20 +0200
Message-ID<rKY6t-4F5-11@gated-at.bofh.it>
In reply to#1424528
Dear Heiko,

On 06/17/2016 07:15 AM, Heiko Stübner wrote:
> Hi William,
>
> Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
>> This patch adds the devicetree documentation required for Rockchip
>> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
>>
>> It supports DRD mode, and could operate in device mode (SS, HS, FS)
>> and host mode (SS, HS, FS, LS).
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
> devicetree binding documentation patches should include the devicetree
> maintainers (scripts/get_maintainer.pl)
I'll add devicetree maintainers in next patch v5.
>
>> ---
>> Changes in v4:
>> - modify commit log, and add phy documentation location (Sergei)
>>
>> Changes in v3:
>> - add dwc3 address (balbi)
>>
>> Changes in v2:
>> - add rockchip,dwc3.txt to Documentation/devicetree/bindings/ (balbi,
> Brian)
>>   .../devicetree/bindings/usb/rockchip,dwc3.txt      | 46
>> ++++++++++++++++++++++ 1 file changed, 46 insertions(+)
>>   create mode 100644
> Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt new file mode
>> 100644
>> index 0000000..0edf013
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> @@ -0,0 +1,46 @@
>> +Rockchip SuperSpeed DWC3 USB SoC controller
>> +
>> +Required properties:
>> +- compatible:	should contain "rockchip,dwc3"
> are you sure this will work for all future socs in the same way? I guess
> doing this as rockchip,rk3399-dwc3 might make our lifes easier down the road
> :-) [both the xilinx and st dwc3 bindings do already that]
I'm not sure that whether our future socs dwc3 will work well in the 
same way.
So I think "rockchip,rk3399-dwc3" is more appropriate.
Thanks very much for your suggestion.
>
>> +- clocks:		A list of phandle + clock-specifier pairs for the
>> +				clocks listed in clock-names
>> +- clock-names:	Should contain the following:
>> +  "clk_usb3otg0_ref"	Controller reference clk
>> +  "clk_usb3otg0_suspend"Controller suspend clk, can use 24 MHz or 32 KHz
>> +  "aclk_usb3"		Master/Core clock, have to be >= 62.5 MHz for SS
> operation
>
> clock names should always be in the scope of the device block (named after
> what it supplies). And looking at the dwc3-xilinx.txt binding, I'd suggest
> getting inspiration from their clock names (bus_clk, ref_clk, suspend_clk or
> so)
I'll fix the clock names next patch v5.
>
>> +Optional clocks:
>> +  "aclk_usb3otg0"	Aclk for specific usb controller clock.
>> +  "aclk_usb3_rksoc_axi_perf"  USB AXI perf clock.  Not present on all
>> platforms.
> The clock names looks pretty strange. What are they for? Especially as
> nothing seems to use them right now.

"aclk_usb3_rksoc_axi_perf", it's the clk for usb3 performance monitor module,
you can refer to the GRF_USB3_PERF_xxx. And we don't use the usb3 performance
monitor control registers right now.

>
>
>> +  "aclk_usb3_grf"	USB grf clock.  Not present on all platforms.
> for my own education, which part of the GRF does this clock supply?

"aclk_usb3_grf", it's the clk for USB3 grf, e.g. GRF_USB3OTGX_CONX

>
>
>> +
>> +Required child node:
>> +A child node must exist to represent the core DWC3 IP block. The name of
>> +the node is not important. The content of the node is defined in dwc3.txt.
>> +
>> +Phy documentation is provided in the following places:
>> +Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
>> +
>> +Example device nodes:
>> +
>> +	usbdrd3_0: usb@fe800000 {
>> +		compatible = "rockchip,dwc3";
>> +		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
>> +			 <&cru ACLK_USB3>, <&cru ACLK_USB3OTG0>,
>> +			 <&cru ACLK_USB3_RKSOC_AXI_PERF>, <&cru ACLK_USB3_GRF>;
>> +		clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
>> +			      "aclk_usb3", "aclk_usb3otg0",
>> +			      "aclk_usb3_rksoc_axi_perf", "aclk_usb3_grf";
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +		status = "disabled";
>> +		usbdrd_dwc3_0: dwc3@fe800000 {
>> +			compatible = "snps,dwc3";
>> +			reg = <0x0 0xfe800000 0x0 0x100000>;
>> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
>> +			dr_mode = "otg";
>> +			status = "disabled";
>> +		};
>> +	};
>
>

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#1426664

FromHeiko Stübner <heiko@sntech.de>
Date2016-06-20 16:50 +0200
Message-ID<rM8Gu-13f-29@gated-at.bofh.it>
In reply to#1424840
Hi William,

Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
> On 06/17/2016 07:15 AM, Heiko Stübner wrote:
> > Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
> >> This patch adds the devicetree documentation required for Rockchip
> >> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
> >> 
> >> It supports DRD mode, and could operate in device mode (SS, HS, FS)
> >> and host mode (SS, HS, FS, LS).
> >> 
> >> Signed-off-by: William Wu <william.wu@rock-chips.com>

[...]

> >> +Optional clocks:
> >> +  "aclk_usb3otg0"	Aclk for specific usb controller clock.

what does this clock do? Also most likely same argument as below.


> >> +  "aclk_usb3_rksoc_axi_perf"  USB AXI perf clock.  Not present on all
> >> platforms.
> > 
> > The clock names looks pretty strange. What are they for? Especially as
> > nothing seems to use them right now.
> 
> "aclk_usb3_rksoc_axi_perf", it's the clk for usb3 performance monitor
> module, you can refer to the GRF_USB3_PERF_xxx. And we don't use the usb3
> performance monitor control registers right now.

ok, then I'd suggest not defining the clock for now.

For one, there are more perf blocks in the GRF (usb3, pcie, hdcp22, gmac, gpu, 
etc) which all seem to share a somewhat similar design, so they will maybe 
result in a separate driver of some form for the performance monitors.

And secondly, it is somewhat easy to add new optional properties, but you 
cannot remove anything defined previously. So if we later decide to handle all 
the performance monitors differently, you can't remove that clock from the 
binding again. (or at least only with quite a bit of hassle).

So as this clock isn't used at all yet, I guess it should not get included 
now.


> >> +  "aclk_usb3_grf"	USB grf clock.  Not present on all platforms.
> > 
> > for my own education, which part of the GRF does this clock supply?
> 
> "aclk_usb3_grf", it's the clk for USB3 grf, e.g. GRF_USB3OTGX_CONX

Hmm, this looks more like it belongs to the otg phy? 
Anyway, also seems unused right now, so same argument as above applies here.


Heiko

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#1427497

FromWilliam Wu <william.wu@rock-chips.com>
Date2016-06-21 11:20 +0200
Message-ID<rMq0F-3PM-17@gated-at.bofh.it>
In reply to#1426664
Dear Heiko,

On 06/20/2016 10:44 PM, Heiko Stübner wrote:
> Hi William,
>
> Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
>> On 06/17/2016 07:15 AM, Heiko Stübner wrote:
>>> Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
>>>> This patch adds the devicetree documentation required for Rockchip
>>>> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
>>>>
>>>> It supports DRD mode, and could operate in device mode (SS, HS, FS)
>>>> and host mode (SS, HS, FS, LS).
>>>>
>>>> Signed-off-by: William Wu <william.wu@rock-chips.com>
> [...]
>
>>>> +Optional clocks:
>>>> +  "aclk_usb3otg0"	Aclk for specific usb controller clock.
> what does this clock do? Also most likely same argument as below.
Here is partial rk3399 clk tree about usb3:

aclk_usb3                       7            7   297000000 0 0
              aclk_usb3_grf                1            1 
297000000          0 0
              aclk_usb3_rksoc_axi_perf     1            1 
297000000          0 0
              aclk_usb3otg1                1            1 
297000000          0 0
              aclk_usb3otg0                1            1 
297000000          0 0
              aclk_usb3_noc                1            1 
297000000          0 0

from the clk tree, and check with our IC designers, we can see that:
1. aclk_usb3 is the parent clk of aclk_usb3****
2. aclk_usb3_grf  is used for both otg0 and otg1 grf, and these usb3 grf 
can be set
to control otg0 and otg1 controller, but not the phy.
3. aclk_usb3otg1 is otg1 controller clk,  aclk_usb3otg0 is otg0 
controller clk.
4. aclk_usb3_rksoc_axi_perf is the clk for usb3 performance monitor module.
5. aclk_usb3_noc is the clk for soc bus interconnect.

>
>>>> +  "aclk_usb3_rksoc_axi_perf"  USB AXI perf clock.  Not present on all
>>>> platforms.
>>> The clock names looks pretty strange. What are they for? Especially as
>>> nothing seems to use them right now.
>> "aclk_usb3_rksoc_axi_perf", it's the clk for usb3 performance monitor
>> module, you can refer to the GRF_USB3_PERF_xxx. And we don't use the usb3
>> performance monitor control registers right now.
> ok, then I'd suggest not defining the clock for now.
>
> For one, there are more perf blocks in the GRF (usb3, pcie, hdcp22, gmac, gpu,
> etc) which all seem to share a somewhat similar design, so they will maybe
> result in a separate driver of some form for the performance monitors.
>
> And secondly, it is somewhat easy to add new optional properties, but you
> cannot remove anything defined previously. So if we later decide to handle all
> the performance monitors differently, you can't remove that clock from the
> binding again. (or at least only with quite a bit of hassle).
>
> So as this clock isn't used at all yet, I guess it should not get included
> now.
Yes, I agree with you. We can remove the aclk_usb3_rksoc_axi_perf right now.
>
>>>> +  "aclk_usb3_grf"	USB grf clock.  Not present on all platforms.
>>> for my own education, which part of the GRF does this clock supply?
>> "aclk_usb3_grf", it's the clk for USB3 grf, e.g. GRF_USB3OTGX_CONX
> Hmm, this looks more like it belongs to the otg phy?
> Anyway, also seems unused right now, so same argument as above applies here.
As I have described above, the "aclk_usb3_grf" is  used for both otg0 
and otg1 grf,
and these usb3 grf can be set to control otg0 and otg1 controller, but 
not the phy.
And we have done a test that remove the grf clk, and the result showed 
that usb3
controller can't work normally. So I think we need the usb3 grf clk.

So about the usb3 controller clk management, I think it should contain 
the following clk:
1.  aclk_usb3otg1
2.  aclk_usb3otg0
3.  aclk_usb3_grf
4.  aclk_usb3_noc
For "aclk_usb3_noc", I discuss with our clk manager, the clk is always 
on before,
but according to upstream maintainer's suggestion, we need to manage the 
noc clk by each module.

and the follow two clk can be removed:
1. aclk_usb3
2. aclk_usb3_rksoc_axi_perf

Is it ok?
>
>
> Heiko
>
>
>

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