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Groups > linux.kernel > #1426424 > unrolled thread
| Started by | Felipe Balbi <balbi@kernel.org> |
|---|---|
| First post | 2016-06-20 11:40 +0200 |
| Last post | 2016-06-20 14:20 +0200 |
| Articles | 3 — 2 participants |
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Re: [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions Felipe Balbi <balbi@kernel.org> - 2016-06-20 11:40 +0200
Re: [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions Roger Quadros <rogerq@ti.com> - 2016-06-20 14:00 +0200
Re: [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions Felipe Balbi <balbi@kernel.org> - 2016-06-20 14:20 +0200
| From | Felipe Balbi <balbi@kernel.org> |
|---|---|
| Date | 2016-06-20 11:40 +0200 |
| Subject | Re: [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions |
| Message-ID | <rM3Qu-6sw-49@gated-at.bofh.it> |
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Hi, Roger Quadros <rogerq@ti.com> writes: > Add OTG and GHWPARAMS6 register definitions > > Signed-off-by: Roger Quadros <rogerq@ti.com> > --- > drivers/usb/dwc3/core.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 83 insertions(+), 1 deletion(-) > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index 8fb6361..32bb7531 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -197,6 +197,15 @@ > #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) > #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) > > +/* Global Status Register */ > +#define DWC3_GSTS_OTG_IP BIT(10) > +#define DWC3_GSTS_BC_IP BIT(9) > +#define DWC3_GSTS_ADP_IP BIT(8) > +#define DWC3_GSTS_HOST_IP BIT(7) > +#define DWC3_GSTS_DEVICE_IP BIT(6) > +#define DWC3_GSTS_CSR_TIMEOUT BIT(5) > +#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) > + > /* Global USB2 PHY Configuration Register */ > #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) > #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) > @@ -269,7 +278,12 @@ > #define DWC3_MAX_HIBER_SCRATCHBUFS 15 > > /* Global HWPARAMS6 Register */ > -#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) > +#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) > +#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) > +#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) > +#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) > +#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) > +#define DWC3_GHWPARAMS6_EN_FPGA BIT(7) Keep consistency, we don't use BIT() here. -- balbi
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| From | Roger Quadros <rogerq@ti.com> |
|---|---|
| Date | 2016-06-20 14:00 +0200 |
| Message-ID | <rM61Y-7K7-47@gated-at.bofh.it> |
| In reply to | #1426424 |
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On 20/06/16 12:28, Felipe Balbi wrote: > > Hi, > > Roger Quadros <rogerq@ti.com> writes: >> Add OTG and GHWPARAMS6 register definitions >> >> Signed-off-by: Roger Quadros <rogerq@ti.com> >> --- >> drivers/usb/dwc3/core.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++- >> 1 file changed, 83 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h >> index 8fb6361..32bb7531 100644 >> --- a/drivers/usb/dwc3/core.h >> +++ b/drivers/usb/dwc3/core.h >> @@ -197,6 +197,15 @@ >> #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) >> #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) >> >> +/* Global Status Register */ >> +#define DWC3_GSTS_OTG_IP BIT(10) >> +#define DWC3_GSTS_BC_IP BIT(9) >> +#define DWC3_GSTS_ADP_IP BIT(8) >> +#define DWC3_GSTS_HOST_IP BIT(7) >> +#define DWC3_GSTS_DEVICE_IP BIT(6) >> +#define DWC3_GSTS_CSR_TIMEOUT BIT(5) >> +#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) >> + >> /* Global USB2 PHY Configuration Register */ >> #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) >> #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) >> @@ -269,7 +278,12 @@ >> #define DWC3_MAX_HIBER_SCRATCHBUFS 15 >> >> /* Global HWPARAMS6 Register */ >> -#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) >> +#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) >> +#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) >> +#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) >> +#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) >> +#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) >> +#define DWC3_GHWPARAMS6_EN_FPGA BIT(7) > > Keep consistency, we don't use BIT() here. > Checkpatch was complaining. But I can revert to the non BIT format for consistency. cheers, -roger
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| From | Felipe Balbi <balbi@kernel.org> |
|---|---|
| Date | 2016-06-20 14:20 +0200 |
| Message-ID | <rM6lj-86N-3@gated-at.bofh.it> |
| In reply to | #1426522 |
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Hi, Roger Quadros <rogerq@ti.com> writes: >> Roger Quadros <rogerq@ti.com> writes: >>> Add OTG and GHWPARAMS6 register definitions >>> >>> Signed-off-by: Roger Quadros <rogerq@ti.com> >>> --- >>> drivers/usb/dwc3/core.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++- >>> 1 file changed, 83 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h >>> index 8fb6361..32bb7531 100644 >>> --- a/drivers/usb/dwc3/core.h >>> +++ b/drivers/usb/dwc3/core.h >>> @@ -197,6 +197,15 @@ >>> #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) >>> #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) >>> >>> +/* Global Status Register */ >>> +#define DWC3_GSTS_OTG_IP BIT(10) >>> +#define DWC3_GSTS_BC_IP BIT(9) >>> +#define DWC3_GSTS_ADP_IP BIT(8) >>> +#define DWC3_GSTS_HOST_IP BIT(7) >>> +#define DWC3_GSTS_DEVICE_IP BIT(6) >>> +#define DWC3_GSTS_CSR_TIMEOUT BIT(5) >>> +#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) >>> + >>> /* Global USB2 PHY Configuration Register */ >>> #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) >>> #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) >>> @@ -269,7 +278,12 @@ >>> #define DWC3_MAX_HIBER_SCRATCHBUFS 15 >>> >>> /* Global HWPARAMS6 Register */ >>> -#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) >>> +#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) >>> +#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) >>> +#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) >>> +#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) >>> +#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) >>> +#define DWC3_GHWPARAMS6_EN_FPGA BIT(7) >> >> Keep consistency, we don't use BIT() here. >> > Checkpatch was complaining. then you should first convert everything to BIT() first, right? > But I can revert to the non BIT format for consistency. works for me. -- balbi
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