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Groups > linux.kernel > #1423851 > unrolled thread

[RESEND PATCH v2 00/13] Clock improvement for video playback

Started byGabriel Fernandez <gabriel.fernandez@linaro.org>
First post2016-06-16 11:30 +0200
Last post2016-06-19 17:00 +0200
Articles 7 — 2 participants

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Contents

  [RESEND PATCH v2 00/13] Clock improvement for video playback Gabriel Fernandez <gabriel.fernandez@linaro.org> - 2016-06-16 11:30 +0200
    [RESEND PATCH v2 11/13] ARM: DT: STiH418: Enable synchronous clock mode for video clocks Gabriel Fernandez <gabriel.fernandez@linaro.org> - 2016-06-16 11:30 +0200
    [RESEND PATCH v2 13/13] ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p Gabriel Fernandez <gabriel.fernandez@linaro.org> - 2016-06-16 11:30 +0200
    [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding of STiH4xx platforms Gabriel Fernandez <gabriel.fernandez@linaro.org> - 2016-06-16 11:30 +0200
      Re: [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding  of STiH4xx platforms Rob Herring <robh@kernel.org> - 2016-06-19 17:30 +0200
        Re: [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding  of STiH4xx platforms Gabriel Fernandez <gabriel.fernandez@linaro.org> - 2016-06-20 09:40 +0200
    Re: [RESEND PATCH v2 01/13] drivers: clk: st: Remove stih415-416  clock support Rob Herring <robh@kernel.org> - 2016-06-19 17:00 +0200

#1423851 — [RESEND PATCH v2 00/13] Clock improvement for video playback

FromGabriel Fernandez <gabriel.fernandez@linaro.org>
Date2016-06-16 11:30 +0200
Subject[RESEND PATCH v2 00/13] Clock improvement for video playback
Message-ID<rKBMB-6A6-5@gated-at.bofh.it>
v2:
  - Simpliflication of clock binding
    remark from Rob https://lkml.org/lkml/2016/5/25/492
  - Suppression of stih415-416 support for the clocks (in order
	to help simplification of clock binding)
    (others patchs for the machine and drivers will come)

This serie allows to increase video resolutions and make audio
adjustment during a video playback.

Gabriel Fernandez (13):
  drivers: clk: st: Remove stih415-416 clock support
  drivers: clk: st: Simplify clock binding of STiH4xx platforms
  drivers: clk: st: Add fs660c32 synthesizer algorithm
  drivers: clk: st: Add clock propagation for audio clocks
  drivers: clk: st: Handle clk synchronous mode for video clocks
  ARM: DT: STiH407: Enable clock propagation for audio clocks
  ARM: DT: STiH410: Enable clock propagation for audio clocks
  ARM: DT: STiH418: Enable clock propagation for audio clocks
  ARM: DT: STiH407: Enable synchronous clock mode for video clocks
  ARM: DT: STiH410: Enable synchronous clock mode for video clocks
  ARM: DT: STiH418: Enable synchronous clock mode for video clocks
  ARM: DT: STi: STiH407: clock configuration to address 720p and 1080p
  ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p

 .../bindings/clock/st/st,clkgen-divmux.txt         |  49 --
 .../devicetree/bindings/clock/st/st,clkgen-mux.txt |  20 +-
 .../devicetree/bindings/clock/st/st,clkgen-pll.txt |  35 +-
 .../bindings/clock/st/st,clkgen-prediv.txt         |  36 -
 .../devicetree/bindings/clock/st/st,clkgen-vcc.txt |  61 --
 .../devicetree/bindings/clock/st/st,clkgen.txt     |  54 +-
 .../devicetree/bindings/clock/st/st,flexgen.txt    |   4 +
 .../devicetree/bindings/clock/st/st,quadfs.txt     |  31 +-
 arch/arm/boot/dts/stih407-clock.dtsi               |   4 +-
 arch/arm/boot/dts/stih407.dtsi                     |  16 +-
 arch/arm/boot/dts/stih410-clock.dtsi               |   4 +-
 arch/arm/boot/dts/stih410.dtsi                     |  16 +-
 arch/arm/boot/dts/stih418-clock.dtsi               |   4 +-
 drivers/clk/st/clk-flexgen.c                       |  61 +-
 drivers/clk/st/clkgen-fsyn.c                       | 481 ++++---------
 drivers/clk/st/clkgen-mux.c                        | 748 +--------------------
 drivers/clk/st/clkgen-pll.c                        | 470 +------------
 17 files changed, 297 insertions(+), 1797 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
 delete mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
 delete mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt

-- 
1.9.1

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#1423852 — [RESEND PATCH v2 11/13] ARM: DT: STiH418: Enable synchronous clock mode for video clocks

FromGabriel Fernandez <gabriel.fernandez@linaro.org>
Date2016-06-16 11:30 +0200
Subject[RESEND PATCH v2 11/13] ARM: DT: STiH418: Enable synchronous clock mode for video clocks
Message-ID<rKBMC-6A6-39@gated-at.bofh.it>
In reply to#1423851
This patch enables the synchronous clock mode for video clocks
on STiH418 board.

Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
 arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 96b4d7b..2254fa5 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -271,7 +271,7 @@
 
 			clk_s_d2_flexgen: clk-s-d2-flexgen {
 				#clock-cells = <1>;
-				compatible = "st,flexgen";
+				compatible = "st,flexgen-video", "st,flexgen";
 
 				clocks = <&clk_s_d2_quadfs 0>,
 					 <&clk_s_d2_quadfs 1>,
-- 
1.9.1

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#1423854 — [RESEND PATCH v2 13/13] ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p

FromGabriel Fernandez <gabriel.fernandez@linaro.org>
Date2016-06-16 11:30 +0200
Subject[RESEND PATCH v2 13/13] ARM: DT: STi: STiH410: clock configuration to address 720p and 1080p
Message-ID<rKBMC-6A6-43@gated-at.bofh.it>
In reply to#1423851
It is necessary to properly configure these clocks in order
to address 720p and 1080p HDMI resolution.

Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
 arch/arm/boot/dts/stih410.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 18ed1ad..7eec729 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -103,7 +103,10 @@
 			#size-cells = <1>;
 
 			assigned-clocks	= <&clk_s_d2_quadfs 0>,
-					  <&clk_s_d2_quadfs 0>,
+					  <&clk_s_d2_quadfs 1>,
+					  <&clk_s_c0_pll1 0>,
+					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
 					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
@@ -113,14 +116,21 @@
 
 			assigned-clock-parents = <0>,
 						 <0>,
+						 <0>,
+						 <&clk_s_c0_pll1 0>,
+						 <&clk_s_c0_pll1 0>,
 						 <&clk_s_d2_quadfs 0>,
-						 <&clk_s_d2_quadfs 0>,
+						 <&clk_s_d2_quadfs 1>,
 						 <&clk_s_d2_quadfs 0>,
 						 <&clk_s_d2_quadfs 0>,
 						 <&clk_s_d2_quadfs 0>,
 						 <&clk_s_d2_quadfs 0>;
 
-			assigned-clock-rates = <297000000>, <297000000>;
+			assigned-clock-rates = <297000000>,
+					       <108000000>,
+					       <0>,
+					       <400000000>,
+					       <400000000>;
 
 			ranges;
 
-- 
1.9.1

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#1423855 — [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding of STiH4xx platforms

FromGabriel Fernandez <gabriel.fernandez@linaro.org>
Date2016-06-16 11:30 +0200
Subject[RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding of STiH4xx platforms
Message-ID<rKBMC-6A6-45@gated-at.bofh.it>
In reply to#1423851
This patch reworks the clock binding to avoid too much detail in DT.
Now we have only compatible string per type of clock
(remark from Rob https://lkml.org/lkml/2016/5/25/492)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
 .../devicetree/bindings/clock/st/st,clkgen-mux.txt |  2 +-
 .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 11 ++--
 .../devicetree/bindings/clock/st/st,clkgen.txt     |  2 +-
 .../devicetree/bindings/clock/st/st,quadfs.txt     |  6 +--
 drivers/clk/st/clkgen-fsyn.c                       | 41 ++++++--------
 drivers/clk/st/clkgen-mux.c                        | 28 ++++------
 drivers/clk/st/clkgen-pll.c                        | 62 ++++++++++------------
 7 files changed, 65 insertions(+), 87 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
index 4d277d6..9a46cb1d7 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
@@ -10,7 +10,7 @@ This binding uses the common clock binding[1].
 Required properties:
 
 - compatible : shall be:
-	"st,stih407-clkgen-a9-mux",	"st,clkgen-mux"
+	"st,stih407-clkgen-a9-mux"
 
 - #clock-cells : from common clock binding; shall be set to 0.
 
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index c9fd674..be0b043 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -9,11 +9,10 @@ Base address is located to the parent node. See clock binding[2]
 Required properties:
 
 - compatible : shall be:
-	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"
-	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"
-	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"
-	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"
-	"st,stih418-plls-c28-a9",	"st,clkgen-plls-c32"
+	"st,clkgen-pll0"
+	"st,clkgen-pll0"
+	"st,stih407-clkgen-plla9"
+	"st,stih418-clkgen-plla9"
 
 - #clock-cells : From common clock binding; shall be set to 1.
 
@@ -29,7 +28,7 @@ Example:
 
 		clockgen_a9_pll: clockgen-a9-pll {
 			#clock-cells = <1>;
-			compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+			compatible = "st,stih407-clkgen-plla9";
 
 			clocks = <&clk_sysin>;
 
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index c764d6b..c35390f 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -48,7 +48,7 @@ Example:
 
 		clk_s_a0_pll: clk-s-a0-pll {
 			#clock-cells = <1>;
-			compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+			compatible = "st,clkgen-pll0";
 
 			clocks = <&clk_sysin>;
 
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
index 6d81b11..d93d493 100644
--- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
@@ -11,8 +11,8 @@ This binding uses the common clock binding[1].
 
 Required properties:
 - compatible : shall be:
-  "st,stih407-quadfs660-C",	"st,quadfs"
-  "st,stih407-quadfs660-D",	"st,quadfs"
+  "st,quadfs"
+  "st,quadfs-pll"
 
 
 - #clock-cells : from common clock binding; shall be set to 1.
@@ -33,7 +33,7 @@ Example:
 
 	clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
 		#clock-cells = <1>;
-		compatible = "st,stih407-quadfs660-C", "st,quadfs";
+		compatible = "st,quadfs-pll";
 		reg = <0x9103000 0x1000>;
 
 		clocks = <&clk_sysin>;
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 4f43b2e..53fd047 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -819,18 +819,6 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
 	return clk;
 }
 
-static const struct of_device_id quadfs_of_match[] = {
-	{
-		.compatible = "st,stih407-quadfs660-C",
-		.data = &st_fs660c32_C
-	},
-	{
-		.compatible = "st,stih407-quadfs660-D",
-		.data = &st_fs660c32_D
-	},
-	{}
-};
-
 static void __init st_of_create_quadfs_fsynths(
 		struct device_node *np, const char *pll_name,
 		struct clkgen_quadfs_data *quadfs, void __iomem *reg,
@@ -886,18 +874,14 @@ static void __init st_of_create_quadfs_fsynths(
 	of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
 }
 
-static void __init st_of_quadfs_setup(struct device_node *np)
+static void __init st_of_quadfs_setup(struct device_node *np,
+		struct clkgen_quadfs_data *data)
 {
-	const struct of_device_id *match;
 	struct clk *clk;
 	const char *pll_name, *clk_parent_name;
 	void __iomem *reg;
 	spinlock_t *lock;
 
-	match = of_match_node(quadfs_of_match, np);
-	if (WARN_ON(!match))
-		return;
-
 	reg = of_iomap(np, 0);
 	if (!reg)
 		return;
@@ -916,8 +900,8 @@ static void __init st_of_quadfs_setup(struct device_node *np)
 
 	spin_lock_init(lock);
 
-	clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name,
-			(struct clkgen_quadfs_data *) match->data, reg, lock);
+	clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, data,
+			reg, lock);
 	if (IS_ERR(clk))
 		goto err_exit;
 	else
@@ -926,11 +910,20 @@ static void __init st_of_quadfs_setup(struct device_node *np)
 			__clk_get_name(clk_get_parent(clk)),
 			(unsigned int)clk_get_rate(clk));
 
-	st_of_create_quadfs_fsynths(np, pll_name,
-				    (struct clkgen_quadfs_data *)match->data,
-				    reg, lock);
+	st_of_create_quadfs_fsynths(np, pll_name, data, reg, lock);
 
 err_exit:
 	kfree(pll_name); /* No longer need local copy of the PLL name */
 }
-CLK_OF_DECLARE(quadfs, "st,quadfs", st_of_quadfs_setup);
+
+static void __init st_of_quadfs660C_setup(struct device_node *np)
+{
+	st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_C);
+}
+CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup);
+
+static void __init st_of_quadfs660D_setup(struct device_node *np)
+{
+	st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_D);
+}
+CLK_OF_DECLARE(quadfs660D, "st,quadfs", st_of_quadfs660D_setup);
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 6fdb1ab..c514d39 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -53,29 +53,13 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
 	.lock = &clkgen_a9_lock,
 };
 
-static const struct of_device_id mux_of_match[] = {
-	{
-		.compatible = "st,stih407-clkgen-a9-mux",
-		.data = &stih407_a9_mux_data,
-	},
-	{}
-};
-static void __init st_of_clkgen_mux_setup(struct device_node *np)
+static void __init st_of_clkgen_mux_setup(struct device_node *np,
+		struct clkgen_mux_data *data)
 {
-	const struct of_device_id *match;
 	struct clk *clk;
 	void __iomem *reg;
 	const char **parents;
 	int num_parents = 0;
-	const struct clkgen_mux_data *data;
-
-	match = of_match_node(mux_of_match, np);
-	if (!match) {
-		pr_err("%s: No matching data\n", __func__);
-		return;
-	}
-
-	data = match->data;
 
 	reg = of_iomap(np, 0);
 	if (!reg) {
@@ -112,4 +96,10 @@ err:
 err_parents:
 	iounmap(reg);
 }
-CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
+
+static void __init st_of_clkgen_a9_mux_setup(struct device_node *np)
+{
+	st_of_clkgen_mux_setup(np, &stih407_a9_mux_data);
+}
+CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
+		st_of_clkgen_a9_mux_setup);
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 224ce9f..8dea6ab 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -702,47 +702,17 @@ static struct clk * __init clkgen_odf_register(const char *parent_name,
 	return clk;
 }
 
-static const struct of_device_id c32_pll_of_match[] = {
-	{
-		.compatible = "st,stih407-plls-c32-a0",
-		.data = &st_pll3200c32_407_a0,
-	},
-	{
-		.compatible = "st,plls-c32-cx_0",
-		.data = &st_pll3200c32_cx_0,
-	},
-	{
-		.compatible = "st,plls-c32-cx_1",
-		.data = &st_pll3200c32_cx_1,
-	},
-	{
-		.compatible = "st,stih407-plls-c32-a9",
-		.data = &st_pll3200c32_407_a9,
-	},
-	{
-		.compatible = "st,stih418-plls-c28-a9",
-		.data = &st_pll4600c28_418_a9,
-	},
-	{}
-};
 
-static void __init clkgen_c32_pll_setup(struct device_node *np)
+static void __init clkgen_c32_pll_setup(struct device_node *np,
+		struct clkgen_pll_data *data)
 {
-	const struct of_device_id *match;
 	struct clk *clk;
 	const char *parent_name, *pll_name;
 	void __iomem *pll_base;
 	int num_odfs, odf;
 	struct clk_onecell_data *clk_data;
-	struct clkgen_pll_data	*data;
 
-	match = of_match_node(c32_pll_of_match, np);
-	if (!match) {
-		pr_err("%s: No matching data\n", __func__);
-		return;
-	}
 
-	data = (struct clkgen_pll_data *) match->data;
 
 	parent_name = of_clk_get_parent_name(np, 0);
 	if (!parent_name)
@@ -796,4 +766,30 @@ err:
 	kfree(clk_data->clks);
 	kfree(clk_data);
 }
-CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup);
+static void __init clkgen_c32_pll0_setup(struct device_node *np)
+{
+	clkgen_c32_pll_setup(np,
+			(struct clkgen_pll_data *) &st_pll3200c32_cx_0);
+}
+CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
+
+static void __init clkgen_c32_pll1_setup(struct device_node *np)
+{
+	clkgen_c32_pll_setup(np,
+			(struct clkgen_pll_data *) &st_pll3200c32_cx_1);
+}
+CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
+
+static void __init clkgen_c32_plla9_setup(struct device_node *np)
+{
+	clkgen_c32_pll_setup(np,
+			(struct clkgen_pll_data *) &st_pll3200c32_407_a9);
+}
+CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
+
+static void __init clkgen_c28_plla9_setup(struct device_node *np)
+{
+	clkgen_c32_pll_setup(np,
+			(struct clkgen_pll_data *) &st_pll4600c28_418_a9);
+}
+CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
-- 
1.9.1

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#1425988 — Re: [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding of STiH4xx platforms

FromRob Herring <robh@kernel.org>
Date2016-06-19 17:30 +0200
SubjectRe: [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding of STiH4xx platforms
Message-ID<rLMPD-46P-1@gated-at.bofh.it>
In reply to#1423855
On Thu, Jun 16, 2016 at 11:20:22AM +0200, Gabriel Fernandez wrote:
> This patch reworks the clock binding to avoid too much detail in DT.
> Now we have only compatible string per type of clock
> (remark from Rob https://lkml.org/lkml/2016/5/25/492)
>

I have no idea what the clock trees and clock controller in these chips 
look like, so it's hard to say if the changes here are good. It still 
looks like things are somewhat fine grained clocks in DT. I'll leave 
it up to the platform maintainers to decide...
 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
>  .../devicetree/bindings/clock/st/st,clkgen-mux.txt |  2 +-
>  .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 11 ++--
>  .../devicetree/bindings/clock/st/st,clkgen.txt     |  2 +-
>  .../devicetree/bindings/clock/st/st,quadfs.txt     |  6 +--
>  drivers/clk/st/clkgen-fsyn.c                       | 41 ++++++--------
>  drivers/clk/st/clkgen-mux.c                        | 28 ++++------
>  drivers/clk/st/clkgen-pll.c                        | 62 ++++++++++------------
>  7 files changed, 65 insertions(+), 87 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> index 4d277d6..9a46cb1d7 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
> @@ -10,7 +10,7 @@ This binding uses the common clock binding[1].
>  Required properties:
>  
>  - compatible : shall be:
> -	"st,stih407-clkgen-a9-mux",	"st,clkgen-mux"
> +	"st,stih407-clkgen-a9-mux"
>  
>  - #clock-cells : from common clock binding; shall be set to 0.
>  
> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> index c9fd674..be0b043 100644
> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
> @@ -9,11 +9,10 @@ Base address is located to the parent node. See clock binding[2]
>  Required properties:
>  
>  - compatible : shall be:
> -	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"
> -	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"
> -	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"
> -	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"
> -	"st,stih418-plls-c28-a9",	"st,clkgen-plls-c32"

> +	"st,clkgen-pll0"
> +	"st,clkgen-pll0"

Repeated. Supposed to be 0 and 1? This seems a bit generic, too.

> +	"st,stih407-clkgen-plla9"
> +	"st,stih418-clkgen-plla9"

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#1426282 — Re: [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding of STiH4xx platforms

FromGabriel Fernandez <gabriel.fernandez@linaro.org>
Date2016-06-20 09:40 +0200
SubjectRe: [RESEND PATCH v2 02/13] drivers: clk: st: Simplify clock binding of STiH4xx platforms
Message-ID<rM1Yl-5hV-1@gated-at.bofh.it>
In reply to#1425988
Hi Rob,

On 19 June 2016 at 17:04, Rob Herring <robh@kernel.org> wrote:
> On Thu, Jun 16, 2016 at 11:20:22AM +0200, Gabriel Fernandez wrote:
>> This patch reworks the clock binding to avoid too much detail in DT.
>> Now we have only compatible string per type of clock
>> (remark from Rob https://lkml.org/lkml/2016/5/25/492)
>>
>
> I have no idea what the clock trees and clock controller in these chips
> look like, so it's hard to say if the changes here are good. It still
> looks like things are somewhat fine grained clocks in DT. I'll leave
> it up to the platform maintainers to decide...
>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> ---
>>  .../devicetree/bindings/clock/st/st,clkgen-mux.txt |  2 +-
>>  .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 11 ++--
>>  .../devicetree/bindings/clock/st/st,clkgen.txt     |  2 +-
>>  .../devicetree/bindings/clock/st/st,quadfs.txt     |  6 +--
>>  drivers/clk/st/clkgen-fsyn.c                       | 41 ++++++--------
>>  drivers/clk/st/clkgen-mux.c                        | 28 ++++------
>>  drivers/clk/st/clkgen-pll.c                        | 62 ++++++++++------------
>>  7 files changed, 65 insertions(+), 87 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> index 4d277d6..9a46cb1d7 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
>> @@ -10,7 +10,7 @@ This binding uses the common clock binding[1].
>>  Required properties:
>>
>>  - compatible : shall be:
>> -     "st,stih407-clkgen-a9-mux",     "st,clkgen-mux"
>> +     "st,stih407-clkgen-a9-mux"
>>
>>  - #clock-cells : from common clock binding; shall be set to 0.
>>
>> diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> index c9fd674..be0b043 100644
>> --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
>> @@ -9,11 +9,10 @@ Base address is located to the parent node. See clock binding[2]
>>  Required properties:
>>
>>  - compatible : shall be:
>> -     "st,stih407-plls-c32-a0",       "st,clkgen-plls-c32"
>> -     "st,stih407-plls-c32-a9",       "st,clkgen-plls-c32"
>> -     "sst,plls-c32-cx_0",            "st,clkgen-plls-c32"
>> -     "sst,plls-c32-cx_1",            "st,clkgen-plls-c32"
>> -     "st,stih418-plls-c28-a9",       "st,clkgen-plls-c32"
>
>> +     "st,clkgen-pll0"
>> +     "st,clkgen-pll0"
>
> Repeated. Supposed to be 0 and 1? This seems a bit generic, too.
Yes you are right, it's 0 and 1.
I wait remarks from Mike or Stephen before send a V3.

Thanks Rob

BR
Gabriel

>
>> +     "st,stih407-clkgen-plla9"
>> +     "st,stih418-clkgen-plla9"

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#1425987 — Re: [RESEND PATCH v2 01/13] drivers: clk: st: Remove stih415-416 clock support

FromRob Herring <robh@kernel.org>
Date2016-06-19 17:00 +0200
SubjectRe: [RESEND PATCH v2 01/13] drivers: clk: st: Remove stih415-416 clock support
Message-ID<rLMmC-3I1-11@gated-at.bofh.it>
In reply to#1423851
On Thu, Jun 16, 2016 at 11:20:21AM +0200, Gabriel Fernandez wrote:
> STiH415 and STiH416 platforms are no longer used.
> these platforms will be deprecated for the next kernel.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
>  .../bindings/clock/st/st,clkgen-divmux.txt         |  49 --
>  .../devicetree/bindings/clock/st/st,clkgen-mux.txt |  18 +-
>  .../devicetree/bindings/clock/st/st,clkgen-pll.txt |  26 +-
>  .../bindings/clock/st/st,clkgen-prediv.txt         |  36 -
>  .../devicetree/bindings/clock/st/st,clkgen-vcc.txt |  61 --
>  .../devicetree/bindings/clock/st/st,clkgen.txt     |  54 +-
>  .../devicetree/bindings/clock/st/st,quadfs.txt     |  27 +-
>  drivers/clk/st/clkgen-fsyn.c                       | 260 --------
>  drivers/clk/st/clkgen-mux.c                        | 726 +--------------------
>  drivers/clk/st/clkgen-pll.c                        | 418 ------------
>  10 files changed, 37 insertions(+), 1638 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
>  delete mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
>  delete mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt

Acked-by: Rob Herring <robh@kernel.org>

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