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| Started by | Shawn Lin <shawn.lin@rock-chips.com> |
|---|---|
| First post | 2016-06-14 02:50 +0200 |
| Last post | 2016-06-16 21:40 +0200 |
| Articles | 4 — 4 participants |
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[PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Shawn Lin <shawn.lin@rock-chips.com> - 2016-06-14 02:50 +0200
Re: [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Doug Anderson <dianders@chromium.org> - 2016-06-14 19:30 +0200
Re: [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Rob Herring <robh@kernel.org> - 2016-06-16 20:50 +0200
Re: [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY Heiko Stübner <heiko@sntech.de> - 2016-06-16 21:40 +0200
| From | Shawn Lin <shawn.lin@rock-chips.com> |
|---|---|
| Date | 2016-06-14 02:50 +0200 |
| Subject | [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY |
| Message-ID | <rJKIh-5BS-15@gated-at.bofh.it> |
This patch adds a binding that describes the Rockchip PCIe PHY
found on Rockchip SoCs PCIe interface.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- add clk and reset description
- remove unit-address
.../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
new file mode 100644
index 0000000..ad55c67
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -0,0 +1,32 @@
+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+ - clocks: Must contain an entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "refclk"
+ - resets: Must contain an entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names: Must be "phy"
+
+Example:
+
+grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ...
+
+ pcie-phy: phy {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <0>;
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ resets = <&cru SRST_PCIEPHY>;
+ reset-names = "phy";
+ };
+};
+
--
2.3.7
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| From | Doug Anderson <dianders@chromium.org> |
|---|---|
| Date | 2016-06-14 19:30 +0200 |
| Subject | Re: [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY |
| Message-ID | <rK0k2-7St-33@gated-at.bofh.it> |
| In reply to | #1421478 |
Hi,
On Mon, Jun 13, 2016 at 5:44 PM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> ---
>
> Changes in v2:
> - add clk and reset description
> - remove unit-address
>
> .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> new file mode 100644
> index 0000000..ad55c67
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> @@ -0,0 +1,32 @@
> +Rockchip PCIE PHY
> +-----------------------
> +
> +Required properties:
> + - compatible: rockchip,rk3399-pcie-phy
> + - #phy-cells: must be 0
> + - clocks: Must contain an entry in clock-names.
> + See ../clocks/clock-bindings.txt for details.
> + - clock-names: Must be "refclk"
> + - resets: Must contain an entry in reset-names.
> + See ../reset/reset.txt for details.
> + - reset-names: Must be "phy"
> +
> +Example:
> +
> +grf: syscon@ff770000 {
> + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ...
> +
> + pcie-phy: phy {
Just calling this node "phy" isn't a good idea. There will be
multiple PHYs under the GRF and they can't all have a subnode named
"phy".
Also: at least in Rockchip device trees usually aliases use
underscores whereas node names use dashes. I'm not actually sure what
the official device tree policy is on this, but it's what I've seen
done. So this should actually be:
pcie_phy: pcie-phy {
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-06-16 20:50 +0200 |
| Subject | Re: [PATCH v2 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY |
| Message-ID | <rKKwx-3rm-19@gated-at.bofh.it> |
| In reply to | #1422127 |
On Tue, Jun 14, 2016 at 10:27:46AM -0700, Doug Anderson wrote:
> Hi,
>
> On Mon, Jun 13, 2016 at 5:44 PM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> > This patch adds a binding that describes the Rockchip PCIe PHY
> > found on Rockchip SoCs PCIe interface.
> >
> > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> >
> > ---
> >
> > Changes in v2:
> > - add clk and reset description
> > - remove unit-address
> >
> > .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++
> > 1 file changed, 32 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > new file mode 100644
> > index 0000000..ad55c67
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > @@ -0,0 +1,32 @@
> > +Rockchip PCIE PHY
> > +-----------------------
> > +
> > +Required properties:
> > + - compatible: rockchip,rk3399-pcie-phy
> > + - #phy-cells: must be 0
> > + - clocks: Must contain an entry in clock-names.
> > + See ../clocks/clock-bindings.txt for details.
> > + - clock-names: Must be "refclk"
> > + - resets: Must contain an entry in reset-names.
> > + See ../reset/reset.txt for details.
> > + - reset-names: Must be "phy"
> > +
> > +Example:
> > +
> > +grf: syscon@ff770000 {
> > + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + ...
> > +
> > + pcie-phy: phy {
>
> Just calling this node "phy" isn't a good idea. There will be
> multiple PHYs under the GRF and they can't all have a subnode named
> "phy".
There's no register range that can be associated with the phy?
>
> Also: at least in Rockchip device trees usually aliases use
> underscores whereas node names use dashes. I'm not actually sure what
> the official device tree policy is on this, but it's what I've seen
> done. So this should actually be:
Labels don't matter as they don't end up in the dtb. Node names should
be generic. though we've only defined a small set of generic names. And
yes, use '-' not '_'.
Rob
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| From | Heiko Stübner <heiko@sntech.de> |
|---|---|
| Date | 2016-06-16 21:40 +0200 |
| Message-ID | <rKLiV-3Wz-15@gated-at.bofh.it> |
| In reply to | #1424346 |
Am Donnerstag, 16. Juni 2016, 13:46:32 schrieb Rob Herring:
> On Tue, Jun 14, 2016 at 10:27:46AM -0700, Doug Anderson wrote:
> > Hi,
> >
> > On Mon, Jun 13, 2016 at 5:44 PM, Shawn Lin <shawn.lin@rock-chips.com>
wrote:
> > > This patch adds a binding that describes the Rockchip PCIe PHY
> > > found on Rockchip SoCs PCIe interface.
> > >
> > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> > >
> > > ---
> > >
> > > Changes in v2:
> > > - add clk and reset description
> > > - remove unit-address
> > >
> > > .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32
> > > ++++++++++++++++++++++ 1 file changed, 32 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt> >
> > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > > b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file
> > > mode 100644
> > > index 0000000..ad55c67
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > > @@ -0,0 +1,32 @@
> > > +Rockchip PCIE PHY
> > > +-----------------------
> > > +
> > > +Required properties:
> > > + - compatible: rockchip,rk3399-pcie-phy
> > > + - #phy-cells: must be 0
> > > + - clocks: Must contain an entry in clock-names.
> > > + See ../clocks/clock-bindings.txt for details.
> > > + - clock-names: Must be "refclk"
> > > + - resets: Must contain an entry in reset-names.
> > > + See ../reset/reset.txt for details.
> > > + - reset-names: Must be "phy"
> > > +
> > > +Example:
> > > +
> > > +grf: syscon@ff770000 {
> > > + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > +
> > > + ...
> > > +
> > > + pcie-phy: phy {
> >
> > Just calling this node "phy" isn't a good idea. There will be
> > multiple PHYs under the GRF and they can't all have a subnode named
> > "phy".
>
> There's no register range that can be associated with the phy?
The pcie phy control bits are sitting in a general (and shared) soc-control
register inside the "General Register Files" (shared for example with some i2s
control bits). As written in a previous version of this binding, my feeling is
that a register range suggests some sort of exclusivity of the area (like the
rk3399 emmc phy occupying a real subset of GRF area), but the pcie phy doesn't
have this.
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