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Groups > linux.kernel > #1420216 > unrolled thread

Re: Using irq-crossbar.c

Started byMarc Zyngier <marc.zyngier@arm.com>
First post2016-06-12 12:10 +0200
Last post2016-06-13 10:00 +0200
Articles 3 — 2 participants

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  Re: Using irq-crossbar.c Marc Zyngier <marc.zyngier@arm.com> - 2016-06-12 12:10 +0200
    Re: Using irq-crossbar.c Mason <slash.tmp@free.fr> - 2016-06-12 16:00 +0200
      Re: Using irq-crossbar.c Marc Zyngier <marc.zyngier@arm.com> - 2016-06-13 10:00 +0200

#1420216 — Re: Using irq-crossbar.c

FromMarc Zyngier <marc.zyngier@arm.com>
Date2016-06-12 12:10 +0200
SubjectRe: Using irq-crossbar.c
Message-ID<rJav8-7mt-13@gated-at.bofh.it>
On Sat, 11 Jun 2016 17:37:51 +0200
Mason <slash.tmp@free.fr> wrote:

> On 11/06/2016 11:58, Marc Zyngier wrote:
> 
> > Mason wrote:
> > 
> >> I think Sebastian is even more baffled by the DT mess
> >> (sorry, intricacies) than I am.
> > 
> > This mess is what has saved us from the apocalypse 5 years ago, and
> > describing a complex system is not easy (what a surprise...).
> 
> The problem with some Linux APIs is that they're logical and obvious
> to people who've been using them for years. For newcomers, it's not
> always so obvious.
> 
> In this specific instance, the problem statement seems rather simple,
> on the surface. An interrupt controller, X=0..127 lines in, Y=0..23
> lines out (connected to GIC interrupt lines 0..23) and "all" we need
> is a way to map Xs to Ys.
> 
> As a first order approximation, it's enough to map all Xs to 0.
> And provide a way for the kernel to check the registers containing
> the bit-vectors indicating which interrupt(s) fired.

If that's what your hardware is, then you are taking the wrong
approach. The irq-crossbar driver does not do that at all: it has x
inputs and y outputs, but connects exactly *one input to one output*.
No multiplexing.

And the hierarchical domain infrastructure enforces a similar property:
a Linux interrupt is dealt with at each level of the hierarchy without
multiplexing: the "irq" is the same, while the "hwirq" varies to
reflect the "input pin" for a given interrupt controller.

In your particular case, you have an evolved chained interrupt
controller, and nothing else.

> 
> > If you just want to apply recipes without understanding the underlying
> > constraints, you're in for a lot of pain.
> 
> For example, the IRQ driver for Tango3/4 calls
> 
> irq_find_mapping
> generic_handle_irq
> irq_desc_get_handler_data
> irq_desc_get_chip
> chained_irq_enter/chained_irq_exit
> irq_setup_alt_chip
> irq_get_domain_generic_chip
> irq_domain_add_linear
> irq_alloc_domain_generic_chips
> irq_set_chained_handler
> irq_set_handler_data
> 
> Taking irq_find_mapping, I see that there's a short comment in
> kernel/irq/irqdomain.c
> 
> /**
>  * irq_find_mapping() - Find a linux irq from an hw irq number.
>  * @domain: domain owning this hardware interrupt
>  * @hwirq: hardware irq number in that domain space
>  */
> 
> Is this Doxygen format? Is there a make target to generate
> some documentation?

Try "make help".

> 
> Other relevant resources, for my own reference:
> 
> https://www.kernel.org/doc/Documentation/IRQ-domain.txt
> https://stackoverflow.com/questions/34371352/what-are-linux-irq-domains-why-are-they-needed
> https://community.nxp.com/thread/332183
> 
> Are there other important kernel documentation?
> 
> >> The base file he was referring to is:
> >>
> >> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/tango4-common.dtsi
> > 
> > I know which file that is, it is mentioned in the diff. I was merely
> > trying to point out the glaring mistakes that could be enough for a
> > interrupt controller hierarchy to be completely non-functional:
> 
> Only the name of the file was provided, not the path. I was not aware
> that you already knew where to find it. I made no claim whatsoever on
> the implementation. In fact, I agree with everything Lennart wrote.
> 
> > - Your crossbar doesn't have a #interrupt-cells property. How do you
> >   expect the interrupt specifiers to be interpreted?
> 
> Why do "fundamental" DT properties start with hash?

Because # is a shorthand for "number of".

> 
> > - You've changed the default interrupt controller to be your crossbar.
> >   Which means that all the sub-nodes are inheriting it. Have you
> >   checked that this was valid for all of these nodes?
> 
> I'm not sure I follow. All platform interrupts flow into the platform
> controller. Maybe other platforms have more complex setups, with
> several cascaded controllers?

Most embedded platforms do.

	M.
-- 
Jazz is not dead. It just smells funny.

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#1420274

FromMason <slash.tmp@free.fr>
Date2016-06-12 16:00 +0200
Message-ID<rJe5I-U8-9@gated-at.bofh.it>
In reply to#1420216
On 12/06/2016 12:00, Marc Zyngier wrote:

> Mason wrote:
> 
>> The problem with some Linux APIs is that they're logical and obvious
>> to people who've been using them for years. For newcomers, it's not
>> always so obvious.
>>
>> In this specific instance, the problem statement seems rather simple,
>> on the surface. An interrupt controller, X=0..127 lines in, Y=0..23
>> lines out (connected to GIC interrupt lines 0..23) and "all" we need
>> is a way to map Xs to Ys.
>>
>> As a first order approximation, it's enough to map all Xs to 0.
>> And provide a way for the kernel to check the registers containing
>> the bit-vectors indicating which interrupt(s) fired.
> 
> If that's what your hardware is, then you are taking the wrong
> approach. The irq-crossbar driver does not do that at all: it has x
> inputs and y outputs, but connects exactly *one input to one output*.
> No multiplexing.

Connecting one input to one output is possible iff x=y right?
(In other words, a bijection.)


> And the hierarchical domain infrastructure enforces a similar property:
> a Linux interrupt is dealt with at each level of the hierarchy without
> multiplexing: the "irq" is the same, while the "hwirq" varies to
> reflect the "input pin" for a given interrupt controller.
> 
> In your particular case, you have an evolved chained interrupt
> controller, and nothing else.

Is it possible to support such an "evolved chained intc" through DT only,
or does it require a few function calls from driver code?


>> Is this Doxygen format? Is there a make target to generate
>> some documentation?
> 
> Try "make help".

Documentation targets:
 Linux kernel internal documentation in different formats:
  htmldocs        - HTML
  pdfdocs         - PDF
  psdocs          - Postscript
  xmldocs         - XML DocBook
  mandocs         - man pages
  installmandocs  - install man pages generated by mandocs
  cleandocs       - clean all generated DocBook files


>>> - You've changed the default interrupt controller to be your crossbar.
>>>   Which means that all the sub-nodes are inheriting it. Have you
>>>   checked that this was valid for all of these nodes?
>>
>> I'm not sure I follow. All platform interrupts flow into the platform
>> controller. Maybe other platforms have more complex setups, with
>> several cascaded controllers?
> 
> Most embedded platforms do.

My imagination is lacking, I don't see why it needs to be more
complex than N platform input lines, and M output lines feeding
into the GIC (with M <= N)

(Our previous intc had N=64 and M=3; the new one has N=128 and M=24)

Regards.

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#1420556

FromMarc Zyngier <marc.zyngier@arm.com>
Date2016-06-13 10:00 +0200
Message-ID<rJuWS-3i5-33@gated-at.bofh.it>
In reply to#1420274
On 12/06/16 14:50, Mason wrote:
> On 12/06/2016 12:00, Marc Zyngier wrote:
> 
>> Mason wrote:
>>
>>> The problem with some Linux APIs is that they're logical and obvious
>>> to people who've been using them for years. For newcomers, it's not
>>> always so obvious.
>>>
>>> In this specific instance, the problem statement seems rather simple,
>>> on the surface. An interrupt controller, X=0..127 lines in, Y=0..23
>>> lines out (connected to GIC interrupt lines 0..23) and "all" we need
>>> is a way to map Xs to Ys.
>>>
>>> As a first order approximation, it's enough to map all Xs to 0.
>>> And provide a way for the kernel to check the registers containing
>>> the bit-vectors indicating which interrupt(s) fired.
>>
>> If that's what your hardware is, then you are taking the wrong
>> approach. The irq-crossbar driver does not do that at all: it has x
>> inputs and y outputs, but connects exactly *one input to one output*.
>> No multiplexing.
> 
> Connecting one input to one output is possible iff x=y right?
> (In other words, a bijection.)

It is *always* possible to connect anything to anything else. You were
assuming that this particular driver was fitting your particular case,
and it is obvious that it is not (iow: the crossbar transformation
cannot be surjective).

>> And the hierarchical domain infrastructure enforces a similar property:
>> a Linux interrupt is dealt with at each level of the hierarchy without
>> multiplexing: the "irq" is the same, while the "hwirq" varies to
>> reflect the "input pin" for a given interrupt controller.
>>
>> In your particular case, you have an evolved chained interrupt
>> controller, and nothing else.
> 
> Is it possible to support such an "evolved chained intc" through DT only,
> or does it require a few function calls from driver code?

There is no such thing as "DT only". You will have to do some actual
irqchip development.

>>>> - You've changed the default interrupt controller to be your crossbar.
>>>>   Which means that all the sub-nodes are inheriting it. Have you
>>>>   checked that this was valid for all of these nodes?
>>>
>>> I'm not sure I follow. All platform interrupts flow into the platform
>>> controller. Maybe other platforms have more complex setups, with
>>> several cascaded controllers?
>>
>> Most embedded platforms do.
> 
> My imagination is lacking, I don't see why it needs to be more
> complex than N platform input lines, and M output lines feeding
> into the GIC (with M <= N)

It is not more complex. It is different.

	M.
-- 
Jazz is not dead. It just smells funny...

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