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[RESEND PATCH 0/3] mtd: nand: standardize ECC maximization

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  [RESEND PATCH 0/3] mtd: nand: standardize ECC maximization Boris Brezillon <boris.brezillon@free-electrons.com> - 2016-06-08 17:10 +0200
    [RESEND PATCH 2/3] mtd: nand: Support maximizing ECC when using software BCH Boris Brezillon <boris.brezillon@free-electrons.com> - 2016-06-08 17:10 +0200
    [RESEND PATCH 3/3] mtd: nand: sunxi: Support ECC maximization Boris Brezillon <boris.brezillon@free-electrons.com> - 2016-06-08 17:10 +0200
    [RESEND PATCH 1/3] mtd: nand: Add an option to maximize the ECC strength Boris Brezillon <boris.brezillon@free-electrons.com> - 2016-06-08 17:10 +0200
      Re: [RESEND PATCH 1/3] mtd: nand: Add an option to maximize the ECC  strength Rob Herring <robh@kernel.org> - 2016-06-10 16:10 +0200

#1417557 — [RESEND PATCH 0/3] mtd: nand: standardize ECC maximization

Hello,

Sorry for the noise, but I forgot to add DT maintainers in Cc.

This series aims at standardizing a feature already supported by
some NAND controller drivers: setting the maximum ECC strength
based on the OOB area size instead of using the ECC strength/step_size
information retrieved from the DT or NAND detection code.

This is particularly useful when the NAND device is used in by a
FS/wear-leveling layer that is not using the OOB area at all (this is
the case of UBI).

Note that drivers already implementing this kind of logic are not
converted to the new approach (because of backward compatibility
concern), but new drivers or drivers that do not already implement
this 'ECC maximization' logic are encouraged to do it.

Regards,

Boris

Boris Brezillon (3):
  mtd: nand: Add an option to maximize the ECC strength
  mtd: nand: Support maximizing ECC when using software BCH
  mtd: nand: sunxi: Support ECC maximization

 Documentation/devicetree/bindings/mtd/nand.txt |  9 ++++++++
 drivers/mtd/nand/nand_base.c                   | 23 ++++++++++++++++++++
 drivers/mtd/nand/sunxi_nand.c                  | 29 ++++++++++++++++++++++++++
 include/linux/mtd/nand.h                       |  1 +
 4 files changed, 62 insertions(+)

-- 
2.7.4

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#1417558 — [RESEND PATCH 2/3] mtd: nand: Support maximizing ECC when using software BCH

Add support for ECC maximization when software BCH with
nand_ooblayout_lp_ops layout is used.
Other cases should be handled by the NAND controller driver.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
 drivers/mtd/nand/nand_base.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d374129..ca4f53d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4224,6 +4224,7 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
 		ecc->write_page_raw = nand_write_page_raw;
 		ecc->read_oob = nand_read_oob_std;
 		ecc->write_oob = nand_write_oob_std;
+
 		/*
 		* Board driver should supply ecc.size and ecc.strength
 		* values to select how many bits are correctable.
@@ -4246,6 +4247,25 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
 			}
 
 			mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
+
+		}
+
+		/*
+		 * We can only maximize ECC config when the default layout is
+		 * used, otherwise we don't know how many bytes can really be
+		 * used.
+		 */
+		if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
+		    ecc->options & NAND_ECC_MAXIMIZE) {
+			int steps, bytes;
+
+			/* Always prefer 1k blocks over 512bytes ones */
+			ecc->size = 1024;
+			steps = mtd->writesize / ecc->size;
+
+			/* Reserve 2 bytes for the BBM */
+			bytes = (mtd->oobsize - 2) / steps;
+			ecc->strength = bytes * 8 / fls(8 * ecc->size);
 		}
 
 		/* See nand_bch_init() for details. */
-- 
2.7.4

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#1417559 — [RESEND PATCH 3/3] mtd: nand: sunxi: Support ECC maximization

Setup the maximum ECC config when NAND_ECC_MAXIMIZE is set.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
 drivers/mtd/nand/sunxi_nand.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 8dfcb65..21dad0b 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1814,6 +1814,35 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
 	if (!data)
 		return -ENOMEM;
 
+	if (ecc->options & NAND_ECC_MAXIMIZE) {
+		int bytes;
+
+		ecc->size = 1024;
+		nsectors = mtd->writesize / ecc->size;
+
+		/* Reserve 2 bytes for the BBM */
+		bytes = (mtd->oobsize - 2) / nsectors;
+
+		/* 4 non-ECC bytes are added before each ECC bytes section */
+		bytes -= 4;
+
+		/* and bytes has to be even. */
+		if (bytes % 2)
+			bytes--;
+
+		ecc->strength = bytes * 8 / fls(8 * ecc->size);
+
+		for (i = 0; i < ARRAY_SIZE(strengths); i++) {
+			if (strengths[i] > ecc->strength)
+				break;
+		}
+
+		if (!i)
+			ecc->strength = 0;
+		else
+			ecc->strength = strengths[i - 1];
+	}
+
 	if (ecc->size != 512 && ecc->size != 1024)
 		return -EINVAL;
 
-- 
2.7.4

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#1417565 — [RESEND PATCH 1/3] mtd: nand: Add an option to maximize the ECC strength

The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.

In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).

Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
 Documentation/devicetree/bindings/mtd/nand.txt | 9 +++++++++
 drivers/mtd/nand/nand_base.c                   | 3 +++
 include/linux/mtd/nand.h                       | 1 +
 3 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index 3733300..b056016 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -35,6 +35,15 @@ Optional NAND chip properties:
 - nand-ecc-step-size: integer representing the number of data bytes
 		      that are covered by a single ECC step.
 
+- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
+		     strength. The maximum ECC strength is both controller and
+		     chip dependent. The controller side has to select the ECC
+		     config providing the best strength and taking the OOB area
+		     size constraint into account.
+		     This is particularly useful when only the in-band area is
+		     used by the upper layers, and you want to make your NAND
+		     as reliable as possible.
+
 The ECC strength and ECC step size properties define the correction capability
 of a controller. Together, they say a controller can correct "{strength} bit
 errors per {size} bytes".
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 0b0dc29..d374129 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4113,6 +4113,9 @@ static int nand_dt_init(struct nand_chip *chip)
 	if (ecc_step > 0)
 		chip->ecc.size = ecc_step;
 
+	if (of_property_read_bool(dn, "nand-ecc-maximize"))
+		chip->ecc.options |= NAND_ECC_MAXIMIZE;
+
 	return 0;
 }
 
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index fbe8e16..737b00d 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -141,6 +141,7 @@ enum nand_ecc_algo {
  * pages and you want to rely on the default implementation.
  */
 #define NAND_ECC_GENERIC_ERASED_CHECK	BIT(0)
+#define NAND_ECC_MAXIMIZE		BIT(1)
 
 /* Bit mask for flags passed to do_nand_read_ecc */
 #define NAND_GET_DEVICE		0x80
-- 
2.7.4

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#1419453 — Re: [RESEND PATCH 1/3] mtd: nand: Add an option to maximize the ECC strength

On Wed, Jun 08, 2016 at 05:04:22PM +0200, Boris Brezillon wrote:
> The generic NAND DT bindings allows one to tweak the ECC strength and
> step size to their need. It can be used to lower the ECC strength to
> match a bootloader/firmware config, but might also be used to get a better
> reliability.
> 
> In the latter case, the user might want to use the maximum ECC strength
> without having to explicitly calculate the exact value (this value not
> only depends on the OOB size, but also on the NAND controller, and can
> be tricky to extract).
> 
> Add a generic 'nand-ecc-maximize' DT property and the associated
> NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
> ECC strength and step-size on their own.
> 
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/mtd/nand.txt | 9 +++++++++

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/mtd/nand/nand_base.c                   | 3 +++
>  include/linux/mtd/nand.h                       | 1 +
>  3 files changed, 13 insertions(+)

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