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[PATCH v7 0/4] usb: dwc3: dual-role support

Started byRoger Quadros <rogerq@ti.com>
First post2016-06-10 15:20 +0200
Last post2016-06-10 15:30 +0200
Articles 5 — 1 participant

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  [PATCH v7 0/4] usb: dwc3: dual-role support Roger Quadros <rogerq@ti.com> - 2016-06-10 15:20 +0200
    [PATCH v7 4/4] ARM: dts: am43xx: Enable dual-role on USB1 Roger Quadros <rogerq@ti.com> - 2016-06-10 15:20 +0200
    [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions Roger Quadros <rogerq@ti.com> - 2016-06-10 15:20 +0200
    [PATCH v7 3/4] ARM: dts: dra7*-evm: Enable dual-role for usb1 Roger Quadros <rogerq@ti.com> - 2016-06-10 15:20 +0200
    Re: [PATCH v7 0/4] usb: dwc3: dual-role support Roger Quadros <rogerq@ti.com> - 2016-06-10 15:30 +0200

#1419391 — [PATCH v7 0/4] usb: dwc3: dual-role support

FromRoger Quadros <rogerq@ti.com>
Date2016-06-10 15:20 +0200
Subject[PATCH v7 0/4] usb: dwc3: dual-role support
Message-ID<rIuvT-527-3@gated-at.bofh.it>
Hi,

This series adds dual role support to dwc3 controller driver.
Series depends on the OTG/dual-role framework [1].

[1] - http://thread.gmane.org/gmane.linux.usb.general/143568

Patches are based on Felipe's balbi/usb.git testing/next

Changelog:

v7:
- rebased to v4.7-rc1 + balbi/usb.git testing/next
- cleaned up otg irq resource code

v6:
- use just otg irq to get otg events and don't depend on extcon at all.
- follow OTG flow in TRM strictly.
- use tracepoints instead of dev_dbg().
- match IRQ flags in dwc3_omap and core.c for shared otg interrupt.

v5: Internal revision. Not sent to mailing list.

v4: first version that was reviewed.

cheers,
-roger


Roger Quadros (4):
  usb: dwc3: core.h: add some register definitions
  usb: dwc3: add dual-role support
  ARM: dts: dra7*-evm: Enable dual-role for usb1
  ARM: dts: am43xx: Enable dual-role on USB1

 arch/arm/boot/dts/am437x-gp-evm.dts     |   5 +-
 arch/arm/boot/dts/am437x-sk-evm.dts     |   5 +-
 arch/arm/boot/dts/am43x-epos-evm.dts    |   5 +-
 arch/arm/boot/dts/dra7-evm.dts          |   5 +-
 arch/arm/boot/dts/dra72-evm-common.dtsi |   5 +-
 drivers/usb/dwc3/core.c                 | 546 +++++++++++++++++++++++++++++++-
 drivers/usb/dwc3/core.h                 | 114 ++++++-
 drivers/usb/dwc3/gadget.c               |   6 +-
 drivers/usb/dwc3/host.c                 |   2 +
 9 files changed, 677 insertions(+), 16 deletions(-)

-- 
2.7.4

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#1419395 — [PATCH v7 4/4] ARM: dts: am43xx: Enable dual-role on USB1

FromRoger Quadros <rogerq@ti.com>
Date2016-06-10 15:20 +0200
Subject[PATCH v7 4/4] ARM: dts: am43xx: Enable dual-role on USB1
Message-ID<rIuvU-527-13@gated-at.bofh.it>
In reply to#1419391
USB1 port is micro-AB type and can function as peripheral
as well as host. Enable dual-role mode for USB1.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/am437x-gp-evm.dts  | 5 ++++-
 arch/arm/boot/dts/am437x-sk-evm.dts  | 5 ++++-
 arch/arm/boot/dts/am43x-epos-evm.dts | 5 ++++-
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 5bcd3aa..d76a885 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -765,7 +765,10 @@
 };
 
 &usb1 {
-	dr_mode = "peripheral";
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index d82dd6e..b11d50e 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -571,8 +571,11 @@
 };
 
 &usb1 {
-	dr_mode = "peripheral";
 	status = "okay";
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&usb1_pins>;
 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 3549b8c..9578602 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -676,8 +676,11 @@
 };
 
 &usb1 {
-	dr_mode = "peripheral";
 	status = "okay";
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
 };
 
 &usb2_phy2 {
-- 
2.7.4

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#1419397 — [PATCH v7 1/4] usb: dwc3: core.h: add some register definitions

FromRoger Quadros <rogerq@ti.com>
Date2016-06-10 15:20 +0200
Subject[PATCH v7 1/4] usb: dwc3: core.h: add some register definitions
Message-ID<rIuvU-527-27@gated-at.bofh.it>
In reply to#1419391
Add OTG and GHWPARAMS6 register definitions

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/usb/dwc3/core.h | 84 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 83 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8fb6361..32bb7531 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -197,6 +197,15 @@
 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
 
+/* Global Status Register */
+#define DWC3_GSTS_OTG_IP	BIT(10)
+#define DWC3_GSTS_BC_IP		BIT(9)
+#define DWC3_GSTS_ADP_IP	BIT(8)
+#define DWC3_GSTS_HOST_IP	BIT(7)
+#define DWC3_GSTS_DEVICE_IP	BIT(6)
+#define DWC3_GSTS_CSR_TIMEOUT	BIT(5)
+#define DWC3_GSTS_BUS_ERR_ADDR_VLD	BIT(4)
+
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
@@ -269,7 +278,12 @@
 #define DWC3_MAX_HIBER_SCRATCHBUFS		15
 
 /* Global HWPARAMS6 Register */
-#define DWC3_GHWPARAMS6_EN_FPGA			(1 << 7)
+#define DWC3_GHWPARAMS6_BCSUPPORT		BIT(14)
+#define DWC3_GHWPARAMS6_OTG3SUPPORT		BIT(13)
+#define DWC3_GHWPARAMS6_ADPSUPPORT		BIT(12)
+#define DWC3_GHWPARAMS6_HNPSUPPORT		BIT(11)
+#define DWC3_GHWPARAMS6_SRPSUPPORT		BIT(10)
+#define DWC3_GHWPARAMS6_EN_FPGA			BIT(7)
 
 /* Global HWPARAMS7 Register */
 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n)	((n) & 0xffff)
@@ -441,6 +455,74 @@
 #define DWC3_DEPCMD_TYPE_BULK		2
 #define DWC3_DEPCMD_TYPE_INTR		3
 
+/* OTG Configuration Register */
+#define DWC3_OCFG_DISPWRCUTTOFF		BIT(5)
+#define DWC3_OCFG_HIBDISMASK		BIT(4)
+#define DWC3_OCFG_SFTRSTMASK		BIT(3)
+#define DWC3_OCFG_OTGVERSION		BIT(2)
+#define DWC3_OCFG_HNPCAP		BIT(1)
+#define DWC3_OCFG_SRPCAP		BIT(0)
+
+/* OTG CTL Register */
+#define DWC3_OCTL_OTG3GOERR		BIT(7)
+#define DWC3_OCTL_PERIMODE		BIT(6)
+#define DWC3_OCTL_PRTPWRCTL		BIT(5)
+#define DWC3_OCTL_HNPREQ		BIT(4)
+#define DWC3_OCTL_SESREQ		BIT(3)
+#define DWC3_OCTL_TERMSELIDPULSE	BIT(2)
+#define DWC3_OCTL_DEVSETHNPEN		BIT(1)
+#define DWC3_OCTL_HSTSETHNPEN		BIT(0)
+
+/* OTG Event Register */
+#define DWC3_OEVT_DEVICEMODE		BIT(31)
+#define DWC3_OEVT_XHCIRUNSTPSET		BIT(27)
+#define DWC3_OEVT_DEVRUNSTPSET		BIT(26)
+#define DWC3_OEVT_HIBENTRY		BIT(25)
+#define DWC3_OEVT_CONIDSTSCHNG		BIT(24)
+#define DWC3_OEVT_HRRCONFNOTIF		BIT(23)
+#define DWC3_OEVT_HRRINITNOTIF		BIT(22)
+#define DWC3_OEVT_ADEVIDLE		BIT(21)
+#define DWC3_OEVT_ADEVBHOSTEND		BIT(20)
+#define DWC3_OEVT_ADEVHOST		BIT(19)
+#define DWC3_OEVT_ADEVHNPCHNG		BIT(18)
+#define DWC3_OEVT_ADEVSRPDET		BIT(17)
+#define DWC3_OEVT_ADEVSESSENDDET	BIT(16)
+#define DWC3_OEVT_BDEVBHOSTEND		BIT(11)
+#define DWC3_OEVT_BDEVHNPCHNG		BIT(10)
+#define DWC3_OEVT_BDEVSESSVLDDET	BIT(9)
+#define DWC3_OEVT_BDEVVBUSCHNG		BIT(8)
+#define DWC3_OEVT_BSESSVLD		BIT(3)
+#define DWC3_OEVT_HSTNEGSTS		BIT(2)
+#define DWC3_OEVT_SESREQSTS		BIT(1)
+#define DWC3_OEVT_ERROR			BIT(0)
+
+/* OTG Event Enable Register */
+#define DWC3_OEVTEN_XHCIRUNSTPSETEN	BIT(27)
+#define DWC3_OEVTEN_DEVRUNSTPSETEN	BIT(26)
+#define DWC3_OEVTEN_HIBENTRYEN		BIT(25)
+#define DWC3_OEVTEN_CONIDSTSCHNGEN	BIT(24)
+#define DWC3_OEVTEN_HRRCONFNOTIFEN	BIT(23)
+#define DWC3_OEVTEN_HRRINITNOTIFEN	BIT(22)
+#define DWC3_OEVTEN_ADEVIDLEEN		BIT(21)
+#define DWC3_OEVTEN_ADEVBHOSTENDEN	BIT(20)
+#define DWC3_OEVTEN_ADEVHOSTEN		BIT(19)
+#define DWC3_OEVTEN_ADEVHNPCHNGEN	BIT(18)
+#define DWC3_OEVTEN_ADEVSRPDETEN	BIT(17)
+#define DWC3_OEVTEN_ADEVSESSENDDETEN	BIT(16)
+#define DWC3_OEVTEN_BDEVHOSTENDEN	BIT(11)
+#define DWC3_OEVTEN_BDEVHNPCHNGEN	BIT(10)
+#define DWC3_OEVTEN_BDEVSESSVLDDETEN	BIT(9)
+#define DWC3_OEVTEN_BDEVVBUSCHNGE	BIT(8)
+
+/* OTG Status Register */
+#define DWC3_OSTS_DEVRUNSTP		BIT(13)
+#define DWC3_OSTS_XHCIRUNSTP		BIT(12)
+#define DWC3_OSTS_PERIPHERALSTATE	BIT(4)
+#define DWC3_OSTS_XHCIPRTPOWER		BIT(3)
+#define DWC3_OSTS_BSESVLD		BIT(2)
+#define DWC3_OSTS_VBUSVLD		BIT(1)
+#define DWC3_OSTS_CONIDSTS		BIT(0)
+
 /* Structures */
 
 struct dwc3_trb;
-- 
2.7.4

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#1419400 — [PATCH v7 3/4] ARM: dts: dra7*-evm: Enable dual-role for usb1

FromRoger Quadros <rogerq@ti.com>
Date2016-06-10 15:20 +0200
Subject[PATCH v7 3/4] ARM: dts: dra7*-evm: Enable dual-role for usb1
Message-ID<rIuvU-527-31@gated-at.bofh.it>
In reply to#1419391
Now that we have dual-role support working at USB core,
enable dual-role support for usb1 controller.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts          | 5 ++++-
 arch/arm/boot/dts/dra72-evm-common.dtsi | 5 ++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index bafcfac..75a4065 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -731,7 +731,10 @@
 };
 
 &usb1 {
-	dr_mode = "peripheral";
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&usb1_pins>;
 };
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 093538e..24ad2ff 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -571,7 +571,10 @@
 };
 
 &usb2 {
-	dr_mode = "host";
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&usb2_pins>;
 };
-- 
2.7.4

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#1419408

FromRoger Quadros <rogerq@ti.com>
Date2016-06-10 15:30 +0200
Message-ID<rIuFz-55o-7@gated-at.bofh.it>
In reply to#1419391
On 10/06/16 16:17, Roger Quadros wrote:
> Hi,
> 
> This series adds dual role support to dwc3 controller driver.
> Series depends on the OTG/dual-role framework [1].
> 
> [1] - http://thread.gmane.org/gmane.linux.usb.general/143568
> 
> Patches are based on Felipe's balbi/usb.git testing/next

This patch is also a pre-requisite for this series.
http://article.gmane.org/gmane.linux.kernel/2240761

> 
> Changelog:
> 
> v7:
> - rebased to v4.7-rc1 + balbi/usb.git testing/next
> - cleaned up otg irq resource code
> 
> v6:
> - use just otg irq to get otg events and don't depend on extcon at all.
> - follow OTG flow in TRM strictly.
> - use tracepoints instead of dev_dbg().
> - match IRQ flags in dwc3_omap and core.c for shared otg interrupt.
> 
> v5: Internal revision. Not sent to mailing list.
> 
> v4: first version that was reviewed.
> 
> cheers,
> -roger
> 
> 
> Roger Quadros (4):
>   usb: dwc3: core.h: add some register definitions
>   usb: dwc3: add dual-role support
>   ARM: dts: dra7*-evm: Enable dual-role for usb1
>   ARM: dts: am43xx: Enable dual-role on USB1
> 
>  arch/arm/boot/dts/am437x-gp-evm.dts     |   5 +-
>  arch/arm/boot/dts/am437x-sk-evm.dts     |   5 +-
>  arch/arm/boot/dts/am43x-epos-evm.dts    |   5 +-
>  arch/arm/boot/dts/dra7-evm.dts          |   5 +-
>  arch/arm/boot/dts/dra72-evm-common.dtsi |   5 +-
>  drivers/usb/dwc3/core.c                 | 546 +++++++++++++++++++++++++++++++-
>  drivers/usb/dwc3/core.h                 | 114 ++++++-
>  drivers/usb/dwc3/gadget.c               |   6 +-
>  drivers/usb/dwc3/host.c                 |   2 +
>  9 files changed, 677 insertions(+), 16 deletions(-)
> 

--
cheers,
-roger

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