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| Started by | Tai Nguyen <ttnguyen@apm.com> |
|---|---|
| First post | 2016-06-10 03:30 +0200 |
| Last post | 2016-06-10 03:30 +0200 |
| Articles | 4 — 2 participants |
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[PATCH v3 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver Tai Nguyen <ttnguyen@apm.com> - 2016-06-10 03:30 +0200
[PATCH v3 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Tai Nguyen <ttnguyen@apm.com> - 2016-06-10 03:30 +0200
Re: [PATCH v3 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Rob Herring <robh@kernel.org> - 2016-06-10 20:00 +0200
[PATCH v3 4/4] arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries Tai Nguyen <ttnguyen@apm.com> - 2016-06-10 03:30 +0200
| From | Tai Nguyen <ttnguyen@apm.com> |
|---|---|
| Date | 2016-06-10 03:30 +0200 |
| Subject | [PATCH v3 0/4] perf: Add APM X-Gene SoC Performance Monitoring Unit driver |
| Message-ID | <rIjqN-6ed-3@gated-at.bofh.it> |
In addition to the X-Gene ARM CPU performance monitoring unit (PMU), there are PMU for the SoC system devices such as L3 cache(s), I/O bridge(s), memory controller bridges and memory. These PMU devices are loosely architected to follow the same model as the PMU for ARM cores. Signed-off-by: Tai Nguyen <ttnguyen@apm.com> --- v3: * Remove index property use in PMU device sub nodes v2: * Use bitmask for event asignned counter mask pmu_dev->cntr_assign_mask * Remove unnecessary spinlocks in perf add/del operations * Remove unnecessary condition checks * Enforce CPU assignment to one CPU for perf operarations * Set the task_ctx_nr to perf_invalid_context for perf driver * Remove irrelevant pt_rregs * Change perf sysfs attributes to be fixed instead of dynamic * Fix checking for an ACPI companion device instead of EFI enable * Add documentation for config/config1 fields format and perf tool example --- Tai Nguyen (4): MAINTAINERS: Add entry for APM X-Gene SoC PMU driver Documentation: Add documentation for APM X-Gene SoC PMU DTS binding perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries .../devicetree/bindings/perf/apm-xgene-pmu.txt | 112 ++ Documentation/perf/xgene-pmu.txt | 48 + MAINTAINERS | 8 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 58 + drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/xgene_pmu.c | 1427 ++++++++++++++++++++ 7 files changed, 1661 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt create mode 100644 Documentation/perf/xgene-pmu.txt create mode 100644 drivers/perf/xgene_pmu.c -- 1.9.1
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| From | Tai Nguyen <ttnguyen@apm.com> |
|---|---|
| Date | 2016-06-10 03:30 +0200 |
| Subject | [PATCH v3 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding |
| Message-ID | <rIjqO-6ed-21@gated-at.bofh.it> |
| In reply to | #1418975 |
Signed-off-by: Tai Nguyen <ttnguyen@apm.com>
---
.../devicetree/bindings/perf/apm-xgene-pmu.txt | 112 +++++++++++++++++++++
1 file changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
new file mode 100644
index 0000000..afb11cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
@@ -0,0 +1,112 @@
+* APM X-Gene SoC PMU bindings
+
+This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
+The following PMU devices are supported:
+
+ L3C - L3 cache controller
+ IOB - IO bridge
+ MCB - Memory controller bridge
+ MC - Memory controller
+
+The following section describes the SoC PMU DT node binding.
+
+Required properties:
+- compatible : Shall be "apm,xgene-pmu" for revision 1 or
+ "apm,xgene-pmu-v2" for revision 2.
+- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
+- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
+- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
+- reg : First resource shall be the CPU bus PMU resource.
+- interrupts : Interrupt-specifier for PMU IRQ.
+
+Required properties for L3C subnode:
+- compatible : Shall be "apm,xgene-pmu-l3c".
+- reg : First resource shall be the L3C PMU resource.
+
+Required properties for IOB subnode:
+- compatible : Shall be "apm,xgene-pmu-iob".
+- reg : First resource shall be the IOB PMU resource.
+
+Required properties for MCB subnode:
+- compatible : Shall be "apm,xgene-pmu-mcb".
+- reg : First resource shall be the MCB PMU resource.
+- enable-bit-index : The bit indicates if the according MCB is enabled.
+
+Required properties for MC subnode:
+- compatible : Shall be "apm,xgene-pmu-mc".
+- reg : First resource shall be the MC PMU resource.
+- enable-bit-index : The bit indicates if the according MC is enabled.
+
+Example:
+ csw: csw@7e200000 {
+ compatible = "apm,xgene-csw", "syscon";
+ reg = <0x0 0x7e200000 0x0 0x1000>;
+ };
+
+ mcba: mcba@7e700000 {
+ compatible = "apm,xgene-mcb", "syscon";
+ reg = <0x0 0x7e700000 0x0 0x1000>;
+ };
+
+ mcbb: mcbb@7e720000 {
+ compatible = "apm,xgene-mcb", "syscon";
+ reg = <0x0 0x7e720000 0x0 0x1000>;
+ };
+
+ pmu: pmu@78810000 {
+ compatible = "apm,xgene-pmu-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ regmap-csw = <&csw>;
+ regmap-mcba = <&mcba>;
+ regmap-mcbb = <&mcbb>;
+ reg = <0x0 0x78810000 0x0 0x1000>;
+ interrupts = <0x0 0x22 0x4>;
+
+ pmul3c@7e610000 {
+ compatible = "apm,xgene-pmu-l3c";
+ reg = <0x0 0x7e610000 0x0 0x1000>;
+ };
+
+ pmuiob@7e940000 {
+ compatible = "apm,xgene-pmu-iob";
+ reg = <0x0 0x7e940000 0x0 0x1000>;
+ };
+
+ pmucmcb@7e710000 {
+ compatible = "apm,xgene-pmu-mcb";
+ reg = <0x0 0x7e710000 0x0 0x1000>;
+ enable-bit-index = <0>;
+ };
+
+ pmucmcb@7e730000 {
+ compatible = "apm,xgene-pmu-mcb";
+ reg = <0x0 0x7e730000 0x0 0x1000>;
+ enable-bit-index = <1>;
+ };
+
+ pmucmc@7e810000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e810000 0x0 0x1000>;
+ enable-bit-index = <0>;
+ };
+
+ pmucmc@7e850000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e850000 0x0 0x1000>;
+ enable-bit-index = <1>;
+ };
+
+ pmucmc@7e890000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e890000 0x0 0x1000>;
+ enable-bit-index = <2>;
+ };
+
+ pmucmc@7e8d0000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e8d0000 0x0 0x1000>;
+ enable-bit-index = <3>;
+ };
+ };
--
1.9.1
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-06-10 20:00 +0200 |
| Subject | Re: [PATCH v3 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding |
| Message-ID | <rIySR-7H3-3@gated-at.bofh.it> |
| In reply to | #1418979 |
On Thu, Jun 09, 2016 at 06:24:50PM -0700, Tai Nguyen wrote: > Signed-off-by: Tai Nguyen <ttnguyen@apm.com> > --- > .../devicetree/bindings/perf/apm-xgene-pmu.txt | 112 +++++++++++++++++++++ > 1 file changed, 112 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt Acked-by: Rob Herring <robh@kernel.org>
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| From | Tai Nguyen <ttnguyen@apm.com> |
|---|---|
| Date | 2016-06-10 03:30 +0200 |
| Subject | [PATCH v3 4/4] arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries |
| Message-ID | <rIjqO-6ed-17@gated-at.bofh.it> |
| In reply to | #1418975 |
Signed-off-by: Tai Nguyen <ttnguyen@apm.com>
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 58 ++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index fe30f76..62806e0 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -566,6 +566,64 @@
};
};
+ pmu: pmu@78810000 {
+ compatible = "apm,xgene-pmu-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ regmap-csw = <&csw>;
+ regmap-mcba = <&mcba>;
+ regmap-mcbb = <&mcbb>;
+ reg = <0x0 0x78810000 0x0 0x1000>;
+ interrupts = <0x0 0x22 0x4>;
+
+ pmul3c@7e610000 {
+ compatible = "apm,xgene-pmu-l3c";
+ reg = <0x0 0x7e610000 0x0 0x1000>;
+ };
+
+ pmuiob@7e940000 {
+ compatible = "apm,xgene-pmu-iob";
+ reg = <0x0 0x7e940000 0x0 0x1000>;
+ };
+
+ pmucmcb@7e710000 {
+ compatible = "apm,xgene-pmu-mcb";
+ reg = <0x0 0x7e710000 0x0 0x1000>;
+ enable-bit-index = <0>;
+ };
+
+ pmucmcb@7e730000 {
+ compatible = "apm,xgene-pmu-mcb";
+ reg = <0x0 0x7e730000 0x0 0x1000>;
+ enable-bit-index = <1>;
+ };
+
+ pmucmc@7e810000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e810000 0x0 0x1000>;
+ enable-bit-index = <0>;
+ };
+
+ pmucmc@7e850000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e850000 0x0 0x1000>;
+ enable-bit-index = <1>;
+ };
+
+ pmucmc@7e890000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e890000 0x0 0x1000>;
+ enable-bit-index = <2>;
+ };
+
+ pmucmc@7e8d0000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e8d0000 0x0 0x1000>;
+ enable-bit-index = <3>;
+ };
+ };
+
pcie0: pcie@1f2b0000 {
status = "disabled";
device_type = "pci";
--
1.9.1
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