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[RFC PATCH 00/15] Exynos big-endian fixes

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  [RFC PATCH 00/15] Exynos big-endian fixes Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 14/15] hwrng: exynos - fixup IO accesors Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian accessors Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian  accessors Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:50 +0200
    [RFC PATCH 11/15] ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 13/15] memory: samsung: endian fixes for IO Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for  endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-09 10:20 +0200
      Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for  endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 12:20 +0200
        Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:50 +0200
    [RFC PATCH 01/15] clock: exynos: fixup endian in pll clk Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 01/15] clock: exynos: fixup endian in pll clk Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-06-10 12:00 +0200
    [RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit functions Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit  functions Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 14:20 +0200
    [RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:50 +0200
    [RFC PATCH 10/15] ARM: EXYNOS: fixup endian in pm/pmu Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:20 +0200
        Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 14:50 +0200
        Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 15:10 +0200
        Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 15:10 +0200
      Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 13:20 +0200
    [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-06-10 12:00 +0200
    [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian Marek Szyprowski <m.szyprowski@samsung.com> - 2016-06-09 09:00 +0200
        Re: [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-09 10:20 +0200
    [RFC PATCH 09/15] ARM: EXYNOS: fixups for big-endian operation Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 12/15] irqchip/s3c24xx: fixup IO accessors for big endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    Re: [RFC PATCH 00/15] Exynos big-endian fixes Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-09 10:10 +0200

Page 2 of 2 — ← Prev page 1 [2]

#1419375 — Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian

On 06/10/2016 03:02 PM, Ben Dooks wrote:
> On 10/06/16 12:16, Krzysztof Kozlowski wrote:
>> On 06/10/2016 01:12 PM, Ben Dooks wrote:
>>> On 08/06/16 19:31, Matthew Leach wrote:
>>>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>>>
>>>> The exynos low-level debug macros need to be fixed if the system is being
>>>> built big endian. Add the necessary endian swaps for accessing the registers
>>>> to get output working again
>>>>
>>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>>> ---
>>>>  arch/arm/include/debug/samsung.S | 8 ++++++++
>>>>  1 file changed, 8 insertions(+)
>>>
>>> Should this go via the maintainer or to RMK?
>>>
>>> If to RMK, then shall I get it submitted (and does anyone else
>>> want to ack?)
>>
>> If there are no objections, I can take it through samsung-soc with other
>> arch/arm/mach-exynos* patches.
>>
>> What I am missing here, is Matthew's Signed-off-by.
>>
>> Matthew, you touched and sent the patch so could you add the Sob?
> 
> I've asked Matthew to re-send the core patches with the signed-off
> sorted out.

Thanks.

> He can also put them on a public facing git server if
> that would be helpful.

No need. I think it will go through separate trees anyway. Except the
change adding ARCH_SUPPORTS_BIG_ENDIAN, I don't see any dependencies.

As for the ARCH_SUPPORTS_BIG_ENDIAN, I think it should be applied when
all necessary drivers are fixed.

Best regards,
Krzysztof

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#1419381 — Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian

On 10/06/16 12:16, Krzysztof Kozlowski wrote:
> On 06/10/2016 01:12 PM, Ben Dooks wrote:
>> On 08/06/16 19:31, Matthew Leach wrote:
>>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>>
>>> The exynos low-level debug macros need to be fixed if the system is being
>>> built big endian. Add the necessary endian swaps for accessing the registers
>>> to get output working again
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> ---
>>>  arch/arm/include/debug/samsung.S | 8 ++++++++
>>>  1 file changed, 8 insertions(+)
>>
>> Should this go via the maintainer or to RMK?
>>
>> If to RMK, then shall I get it submitted (and does anyone else
>> want to ack?)
> 
> If there are no objections, I can take it through samsung-soc with other
> arch/arm/mach-exynos* patches.
> 
> What I am missing here, is Matthew's Signed-off-by.
> 
> Matthew, you touched and sent the patch so could you add the Sob?

I've asked Matthew to re-send the core patches with the signed-off
sorted out. He can also put them on a public facing git server if
that would be helpful.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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#1419274 — Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian

On 08/06/16 19:31, Matthew Leach wrote:
> From: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> The exynos low-level debug macros need to be fixed if the system is being
> built big endian. Add the necessary endian swaps for accessing the registers
> to get output working again
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>  arch/arm/include/debug/samsung.S | 8 ++++++++
>  1 file changed, 8 insertions(+)

Should this go via the maintainer or to RMK?

If to RMK, then shall I get it submitted (and does anyone else
want to ack?)

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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#1417768 — [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be

Use the byte-order aware big endian accessors, allowing for kernels
running under big-endian.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
---
CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Tomasz Figa <tomasz.figa@gmail.com>
CC: Michael Turquette <mturquette@baylibre.com>
CC: Stephen Boyd <sboyd@codeaurora.org>
CC: Kukjin Kim <kgene@kernel.org>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: linux-samsung-soc@vger.kernel.org
CC: linux-clk@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-kernel@vger.kernel.org
---
 drivers/clk/samsung/clk-exynos4.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7b3d0f9..35a977d 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1375,12 +1375,12 @@ static void __init exynos4x12_core_down_clock(void)
 	if (num_possible_cpus() == 4)
 		tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
 		       PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
-	__raw_writel(tmp, reg_base + PWR_CTRL1);
+	writel_relaxed(tmp, reg_base + PWR_CTRL1);
 
 	/*
 	 * Disable the clock up feature in case it was enabled by bootloader.
 	 */
-	__raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
+	writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
 }
 
 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0)	\
-- 
2.8.3

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#1419187 — Re: [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be

On 06/08/2016 08:30 PM, Matthew Leach wrote:
> Use the byte-order aware big endian accessors, allowing for kernels
> running under big-endian.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>

Patch applied, thanks.

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#1417770 — [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian

From: Ben Dooks <ben.dooks@codethink.co.uk>

Add initial support for big endian by always writing the pte
in le32. Note, revisit if hardware capable of doing big endian
fetches.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org (open list)
---
 drivers/iommu/exynos-iommu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 5ecc86c..dd8b3b3 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -54,6 +54,10 @@ typedef u32 sysmmu_pte_t;
 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
 
+#ifdef CONFIG_BIG_ENDIAN
+#warning "revisit driver if we can enable big-endian ptes"
+#endif
+
 /*
  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  * v5.0 introduced support for 36bit physical address space by shifting
@@ -716,7 +720,7 @@ static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 {
 	dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 				DMA_TO_DEVICE);
-	*ent = val;
+	*ent = cpu_to_le32(val);
 	dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 				   DMA_TO_DEVICE);
 }
-- 
2.8.3

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#1418109 — Re: [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian

Hi


On 2016-06-08 20:31, Matthew Leach wrote:
> From: Ben Dooks <ben.dooks@codethink.co.uk>
>
> Add initial support for big endian by always writing the pte
> in le32. Note, revisit if hardware capable of doing big endian
> fetches.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>

Just to keep my curiosity satisfied - what's the reason to use
big-endian on ARM?

Good luck with fixing the kernel and userspace codes, which usually
assume little-endian is the only possible order!

> ---
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: iommu@lists.linux-foundation.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-samsung-soc@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org (open list)
> ---
>   drivers/iommu/exynos-iommu.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
> index 5ecc86c..dd8b3b3 100644
> --- a/drivers/iommu/exynos-iommu.c
> +++ b/drivers/iommu/exynos-iommu.c
> @@ -54,6 +54,10 @@ typedef u32 sysmmu_pte_t;
>   #define lv2ent_small(pent) ((*(pent) & 2) == 2)
>   #define lv2ent_large(pent) ((*(pent) & 3) == 1)
>   
> +#ifdef CONFIG_BIG_ENDIAN
> +#warning "revisit driver if we can enable big-endian ptes"
> +#endif
> +

This warning can be removed. There is no way to force SYSMMU to operate with
big-endian PTEs according to the datasheet.

>   /*
>    * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
>    * v5.0 introduced support for 36bit physical address space by shifting
> @@ -716,7 +720,7 @@ static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
>   {
>   	dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
>   				DMA_TO_DEVICE);
> -	*ent = val;
> +	*ent = cpu_to_le32(val);
>   	dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
>   				   DMA_TO_DEVICE);
>   }

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

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#1418160 — Re: [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian

On 09/06/16 07:51, Marek Szyprowski wrote:
> Hi
> 
> 
> On 2016-06-08 20:31, Matthew Leach wrote:
>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>
>> Add initial support for big endian by always writing the pte
>> in le32. Note, revisit if hardware capable of doing big endian
>> fetches.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
> 
> Just to keep my curiosity satisfied - what's the reason to use
> big-endian on ARM?

Because we can. It was interesting to try.

> Good luck with fixing the kernel and userspace codes, which usually
> assume little-endian is the only possible order!

We did a BE8 build of the baserock userspace a year or two ago
and found mostly it just worked. I think Matt is using that image
for testing the work he's been doing.

I've no idea if we would ever bother trying to build Debian for BE8
or similar, as not sure it would be worth trying.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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#1417771 — [RFC PATCH 09/15] ARM: EXYNOS: fixups for big-endian operation

From: Ben Dooks <ben.dooks@codethink.co.uk>

If the kernel is built big endian, then using the __raw read and write IO
accessors is not going to work as they end up writing big-endian data to
little-endian IO registers. Fix this by using the readl and writel relaxed
versions which ensure little endian IO.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/mach-exynos/firmware.c | 16 ++++++++--------
 arch/arm/mach-exynos/headsmp.S  |  3 +++
 arch/arm/mach-exynos/platsmp.c  |  4 ++--
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 1bfd1b0..96b5e92 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -41,9 +41,9 @@ static int exynos_do_idle(unsigned long mode)
 	case FW_DO_IDLE_AFTR:
 		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 			exynos_save_cp15();
-		__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
+		writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
 			     sysram_ns_base_addr + 0x24);
-		__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
+		writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
 		if (soc_is_exynos3250()) {
 			flush_cache_all();
 			exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
@@ -97,7 +97,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 	if (soc_is_exynos4412())
 		boot_reg += 4 * cpu;
 
-	__raw_writel(boot_addr, boot_reg);
+	writel_relaxed(boot_addr, boot_reg);
 	return 0;
 }
 
@@ -113,7 +113,7 @@ static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
 	if (soc_is_exynos4412())
 		boot_reg += 4 * cpu;
 
-	*boot_addr = __raw_readl(boot_reg);
+	*boot_addr = readl_relaxed(boot_reg);
 	return 0;
 }
 
@@ -234,20 +234,20 @@ void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
 {
 	unsigned int tmp;
 
-	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+	tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
 
 	if (mode & BOOT_MODE_MASK)
 		tmp &= ~BOOT_MODE_MASK;
 
 	tmp |= mode;
-	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+	writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 }
 
 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
 {
 	unsigned int tmp;
 
-	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+	tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
 	tmp &= ~mode;
-	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+	writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 }
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index b54f970..d3d24ab 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -12,12 +12,15 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
 /*
  * exynos4 specific entry point for secondary CPUs.  This provides
  * a "holding pen" into which all secondary cores are held until we're
  * ready for them to initialise.
  */
 ENTRY(exynos4_secondary_startup)
+ARM_BE8(setend	be)
 	mrc	p15, 0, r0, c0, c0, 5
 	and	r0, r0, #15
 	adr	r4, 1f
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 85c3be6..98ffe1e 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -264,7 +264,7 @@ int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
 			ret = PTR_ERR(boot_reg);
 			goto fail;
 		}
-		__raw_writel(boot_addr, boot_reg);
+		writel_relaxed(boot_addr, boot_reg);
 		ret = 0;
 	}
 fail:
@@ -289,7 +289,7 @@ int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
 			ret = PTR_ERR(boot_reg);
 			goto fail;
 		}
-		*boot_addr = __raw_readl(boot_reg);
+		*boot_addr = readl_relaxed(boot_reg);
 		ret = 0;
 	}
 fail:
-- 
2.8.3

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#1417772 — [RFC PATCH 12/15] irqchip/s3c24xx: fixup IO accessors for big endian

From: Ben Dooks <ben.dooks@codethink.co.uk>

Instead of using the __raw accesors, use the _relaxed versions
to deal with any issues due to endian-ness of the CPU.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

---
CC: Thomas Gleixner <tglx@linutronix.de> (maintainer:IRQCHIP DRIVERS)
CC: Jason Cooper <jason@lakedaemon.net> (maintainer:IRQCHIP DRIVERS)
CC: Marc Zyngier <marc.zyngier@arm.com> (maintainer:IRQCHIP DRIVERS)
CC: linux-kernel@vger.kernel.org (open list:IRQCHIP DRIVERS)
CC: linux-arm-kernel@lists.infradead.org
---
 drivers/irqchip/irq-s3c24xx.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c
index 5dc5a76..c25ce5a 100644
--- a/drivers/irqchip/irq-s3c24xx.c
+++ b/drivers/irqchip/irq-s3c24xx.c
@@ -92,9 +92,9 @@ static void s3c_irq_mask(struct irq_data *data)
 	unsigned long mask;
 	unsigned int irqno;
 
-	mask = __raw_readl(intc->reg_mask);
+	mask = readl_relaxed(intc->reg_mask);
 	mask |= (1UL << irq_data->offset);
-	__raw_writel(mask, intc->reg_mask);
+	writel_relaxed(mask, intc->reg_mask);
 
 	if (parent_intc) {
 		parent_data = &parent_intc->irqs[irq_data->parent_irq];
@@ -119,9 +119,9 @@ static void s3c_irq_unmask(struct irq_data *data)
 	unsigned long mask;
 	unsigned int irqno;
 
-	mask = __raw_readl(intc->reg_mask);
+	mask = readl_relaxed(intc->reg_mask);
 	mask &= ~(1UL << irq_data->offset);
-	__raw_writel(mask, intc->reg_mask);
+	writel_relaxed(mask, intc->reg_mask);
 
 	if (parent_intc) {
 		irqno = irq_find_mapping(parent_intc->domain,
@@ -136,9 +136,9 @@ static inline void s3c_irq_ack(struct irq_data *data)
 	struct s3c_irq_intc *intc = irq_data->intc;
 	unsigned long bitval = 1UL << irq_data->offset;
 
-	__raw_writel(bitval, intc->reg_pending);
+	writel_relaxed(bitval, intc->reg_pending);
 	if (intc->reg_intpnd)
-		__raw_writel(bitval, intc->reg_intpnd);
+		writel_relaxed(bitval, intc->reg_intpnd);
 }
 
 static int s3c_irq_type(struct irq_data *data, unsigned int type)
@@ -172,9 +172,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
 	unsigned long newvalue = 0, value;
 
 	/* Set the GPIO to external interrupt mode */
-	value = __raw_readl(gpcon_reg);
+	value = readl_relaxed(gpcon_reg);
 	value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
-	__raw_writel(value, gpcon_reg);
+	writel_relaxed(value, gpcon_reg);
 
 	/* Set the external interrupt to pointed trigger type */
 	switch (type)
@@ -208,9 +208,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
 			return -EINVAL;
 	}
 
-	value = __raw_readl(extint_reg);
+	value = readl_relaxed(extint_reg);
 	value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
-	__raw_writel(value, extint_reg);
+	writel_relaxed(value, extint_reg);
 
 	return 0;
 }
@@ -315,8 +315,8 @@ static void s3c_irq_demux(struct irq_desc *desc)
 
 	chained_irq_enter(chip, desc);
 
-	src = __raw_readl(sub_intc->reg_pending);
-	msk = __raw_readl(sub_intc->reg_mask);
+	src = readl_relaxed(sub_intc->reg_pending);
+	msk = readl_relaxed(sub_intc->reg_mask);
 
 	src &= ~msk;
 	src &= irq_data->sub_bits;
@@ -337,7 +337,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
 	int pnd;
 	int offset;
 
-	pnd = __raw_readl(intc->reg_intpnd);
+	pnd = readl_relaxed(intc->reg_intpnd);
 	if (!pnd)
 		return false;
 
@@ -352,7 +352,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
 	 *
 	 * Thanks to Klaus, Shannon, et al for helping to debug this problem
 	 */
-	offset = __raw_readl(intc->reg_intpnd + 4);
+	offset = readl_relaxed(intc->reg_intpnd + 4);
 
 	/* Find the bit manually, when the offset is wrong.
 	 * The pending register only ever contains the one bit of the next
@@ -406,7 +406,7 @@ int s3c24xx_set_fiq(unsigned int irq, bool on)
 		intmod = 0;
 	}
 
-	__raw_writel(intmod, S3C2410_INTMOD);
+	writel_relaxed(intmod, S3C2410_INTMOD);
 	return 0;
 }
 
@@ -508,14 +508,14 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
 
 	last = 0;
 	for (i = 0; i < 4; i++) {
-		pend = __raw_readl(reg_source);
+		pend = readl_relaxed(reg_source);
 
 		if (pend == 0 || pend == last)
 			break;
 
-		__raw_writel(pend, intc->reg_pending);
+		writel_relaxed(pend, intc->reg_pending);
 		if (intc->reg_intpnd)
-			__raw_writel(pend, intc->reg_intpnd);
+			writel_relaxed(pend, intc->reg_intpnd);
 
 		pr_info("irq: clearing pending status %08x\n", (int)pend);
 		last = pend;
-- 
2.8.3

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#1418152

On 08/06/16 19:30, Matthew Leach wrote:
> Hi all,
> 
> I've been working with Ben Dooks to get a big-endian kernel working on
> my Exynos 4412 board.  Primarily this series consists of:
> 
>   - Replacing the __raw_{read,write}l accessors, which aren't
>     endian-clean, with their respective {read,write}l_relaxed versions
>     across various drivers.
> 
>   - Adding endian-aware {set,clear}_bit functions to the Exynos serial
>     driver as the __{set,clear}_bit() functions aren't endian-clean.
> 
>   - Make the low-level Exynos debug printing macros endian-clean.
> 
> There may well be other things that are broken under BE that we've not
> tested but this series should be enough to allow a board to boot
> user-space to a login prompt.

The only nit is the use of "be", it would be nicer to either use
BE8 consistently, or go for "big endian".

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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