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Groups > linux.kernel > #1417756 > unrolled thread

[RFC PATCH 00/15] Exynos big-endian fixes

Started byMatthew Leach <matthew@mattleach.net>
First post2016-06-08 20:40 +0200
Last post2016-06-09 10:10 +0200
Articles 20 on this page of 31 — 5 participants

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  [RFC PATCH 00/15] Exynos big-endian fixes Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 14/15] hwrng: exynos - fixup IO accesors Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian accessors Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian  accessors Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:50 +0200
    [RFC PATCH 11/15] ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 13/15] memory: samsung: endian fixes for IO Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for  endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-09 10:20 +0200
      Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for  endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 12:20 +0200
        Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:50 +0200
    [RFC PATCH 01/15] clock: exynos: fixup endian in pll clk Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 01/15] clock: exynos: fixup endian in pll clk Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-06-10 12:00 +0200
    [RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit functions Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit  functions Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 14:20 +0200
    [RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:50 +0200
    [RFC PATCH 10/15] ARM: EXYNOS: fixup endian in pm/pmu Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 13:20 +0200
        Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 14:50 +0200
        Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-06-10 15:10 +0200
        Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 15:10 +0200
      Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-10 13:20 +0200
    [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-06-10 12:00 +0200
    [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
      Re: [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian Marek Szyprowski <m.szyprowski@samsung.com> - 2016-06-09 09:00 +0200
        Re: [RFC PATCH 15/15] iommu/exynos: update to use iommu big-endian Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-09 10:20 +0200
    [RFC PATCH 09/15] ARM: EXYNOS: fixups for big-endian operation Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    [RFC PATCH 12/15] irqchip/s3c24xx: fixup IO accessors for big endian Matthew Leach <matthew@mattleach.net> - 2016-06-08 20:40 +0200
    Re: [RFC PATCH 00/15] Exynos big-endian fixes Ben Dooks <ben.dooks@codethink.co.uk> - 2016-06-09 10:10 +0200

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#1417756 — [RFC PATCH 00/15] Exynos big-endian fixes

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 00/15] Exynos big-endian fixes
Message-ID<rHQyt-3JS-5@gated-at.bofh.it>
Hi all,

I've been working with Ben Dooks to get a big-endian kernel working on
my Exynos 4412 board.  Primarily this series consists of:

  - Replacing the __raw_{read,write}l accessors, which aren't
    endian-clean, with their respective {read,write}l_relaxed versions
    across various drivers.

  - Adding endian-aware {set,clear}_bit functions to the Exynos serial
    driver as the __{set,clear}_bit() functions aren't endian-clean.

  - Make the low-level Exynos debug printing macros endian-clean.

There may well be other things that are broken under BE that we've not
tested but this series should be enough to allow a board to boot
user-space to a login prompt.

Comments/feedback welcome!

Thanks,
Matt

Ben Dooks (9):
  ARM: exynos: fixup debug macros for big-endian
  ARM: samsung: fixup endian issues in cpu detection
  ARM: EXYNOS: fixups for big-endian operation
  ARM: EXYNOS: fixup endian in pm/pmu
  ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly
  irqchip/s3c24xx: fixup IO accessors for big endian
  memory: samsung: endian fixes for IO
  hwrng: exynos - fixup IO accesors
  iommu/exynos: update to use iommu big-endian

Matthew Leach (6):
  clock: exynos: fixup endian in pll clk
  clocksource: samsung_pwm_timer: fix endian accessors
  clk: samsung: exynos4: fixup reg access on be
  irqchip: exynos_combiner: fixup reg access on be
  tty: serial: samsung: fixup accessors for endian
  tty: serial: samsung: add byte-order aware bit functions

 arch/arm/include/debug/samsung.S        |   8 +++
 arch/arm/mach-exynos/Kconfig            |   1 +
 arch/arm/mach-exynos/common.h           |   4 +-
 arch/arm/mach-exynos/firmware.c         |  16 ++---
 arch/arm/mach-exynos/headsmp.S          |   3 +
 arch/arm/mach-exynos/platsmp.c          |   4 +-
 arch/arm/mach-exynos/pm.c               |   4 +-
 arch/arm/mach-exynos/pm_domains.c       |   6 +-
 arch/arm/plat-samsung/cpu.c             |   8 +--
 drivers/char/hw_random/exynos-rng.c     |   4 +-
 drivers/clk/samsung/clk-exynos4.c       |   4 +-
 drivers/clk/samsung/clk-pll.c           | 122 ++++++++++++++++----------------
 drivers/clocksource/samsung_pwm_timer.c |  16 ++---
 drivers/iommu/exynos-iommu.c            |   6 +-
 drivers/irqchip/exynos-combiner.c       |  14 ++--
 drivers/irqchip/irq-s3c24xx.c           |  36 +++++-----
 drivers/memory/samsung/exynos-srom.c    |   6 +-
 drivers/tty/serial/samsung.c            |  16 ++---
 drivers/tty/serial/samsung.h            |  33 ++++++++-
 19 files changed, 177 insertions(+), 134 deletions(-)

-- 
2.8.3

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#1417757 — [RFC PATCH 14/15] hwrng: exynos - fixup IO accesors

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 14/15] hwrng: exynos - fixup IO accesors
Message-ID<rHQyt-3JS-9@gated-at.bofh.it>
In reply to#1417756
From: Ben Dooks <ben.dooks@codethink.co.uk>

The __raw IO functions are not endian safe, so use the readl_relaxed
and writel_relaxed versions of these.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
CC: Matt Mackall <mpm@selenic.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: linux-crypto@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-samsung-soc@vger.kernel.org
---
 drivers/char/hw_random/exynos-rng.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/char/hw_random/exynos-rng.c b/drivers/char/hw_random/exynos-rng.c
index ed44561..23d3585 100644
--- a/drivers/char/hw_random/exynos-rng.c
+++ b/drivers/char/hw_random/exynos-rng.c
@@ -45,12 +45,12 @@ struct exynos_rng {
 
 static u32 exynos_rng_readl(struct exynos_rng *rng, u32 offset)
 {
-	return	__raw_readl(rng->mem + offset);
+	return	readl_relaxed(rng->mem + offset);
 }
 
 static void exynos_rng_writel(struct exynos_rng *rng, u32 val, u32 offset)
 {
-	__raw_writel(val, rng->mem + offset);
+	writel_relaxed(val, rng->mem + offset);
 }
 
 static int exynos_rng_configure(struct exynos_rng *exynos_rng)
-- 
2.8.3

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#1417758 — [RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian accessors

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian accessors
Message-ID<rHQyu-3JS-29@gated-at.bofh.it>
In reply to#1417756
Fix the Samsung pwm timer access code to deal with kernels built for big
endian operation.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
---
CC: Daniel Lezcano <daniel.lezcano@linaro.org>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: linux-kernel@vger.kernel.org
---
 drivers/clocksource/samsung_pwm_timer.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 9502bc4..47e0515 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -130,9 +130,9 @@ static void samsung_time_stop(unsigned int channel)
 
 	spin_lock_irqsave(&samsung_pwm_lock, flags);
 
-	tcon = __raw_readl(pwm.base + REG_TCON);
+	tcon = readl_relaxed(pwm.base + REG_TCON);
 	tcon &= ~TCON_START(channel);
-	__raw_writel(tcon, pwm.base + REG_TCON);
+	writel_relaxed(tcon, pwm.base + REG_TCON);
 
 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 }
@@ -148,14 +148,14 @@ static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
 
 	spin_lock_irqsave(&samsung_pwm_lock, flags);
 
-	tcon = __raw_readl(pwm.base + REG_TCON);
+	tcon = readl_relaxed(pwm.base + REG_TCON);
 
 	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
 	tcon |= TCON_MANUALUPDATE(tcon_chan);
 
-	__raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
-	__raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
-	__raw_writel(tcon, pwm.base + REG_TCON);
+	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
+	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
+	writel_relaxed(tcon, pwm.base + REG_TCON);
 
 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 }
@@ -170,7 +170,7 @@ static void samsung_time_start(unsigned int channel, bool periodic)
 
 	spin_lock_irqsave(&samsung_pwm_lock, flags);
 
-	tcon = __raw_readl(pwm.base + REG_TCON);
+	tcon = readl_relaxed(pwm.base + REG_TCON);
 
 	tcon &= ~TCON_MANUALUPDATE(channel);
 	tcon |= TCON_START(channel);
@@ -180,7 +180,7 @@ static void samsung_time_start(unsigned int channel, bool periodic)
 	else
 		tcon &= ~TCON_AUTORELOAD(channel);
 
-	__raw_writel(tcon, pwm.base + REG_TCON);
+	writel_relaxed(tcon, pwm.base + REG_TCON);
 
 	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
 }
-- 
2.8.3

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#1419301 — Re: [RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian accessors

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-06-10 13:50 +0200
SubjectRe: [RFC PATCH 02/15] clocksource: samsung_pwm_timer: fix endian accessors
Message-ID<rIt6O-41N-13@gated-at.bofh.it>
In reply to#1417758
On 06/08/2016 08:30 PM, Matthew Leach wrote:
> Fix the Samsung pwm timer access code to deal with kernels built for big
> endian operation.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>
> ---
> CC: Daniel Lezcano <daniel.lezcano@linaro.org>
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: linux-kernel@vger.kernel.org
> ---
>  drivers/clocksource/samsung_pwm_timer.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

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#1417760 — [RFC PATCH 11/15] ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 11/15] ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly
Message-ID<rHQyu-3JS-23@gated-at.bofh.it>
In reply to#1417756
From: Ben Dooks <ben.dooks@codethink.co.uk>

Now the initial fixes have the big-endian code working on EXYNOS, make sure
we explicitly mark our arch as being big endian capable.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/mach-exynos/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e65aa7d..14906bf 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -13,6 +13,7 @@ menuconfig ARCH_EXYNOS
 	select ARCH_HAS_BANDGAP
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select ARM_AMBA
 	select ARM_GIC
 	select COMMON_CLK_SAMSUNG
-- 
2.8.3

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#1417761 — [RFC PATCH 13/15] memory: samsung: endian fixes for IO

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 13/15] memory: samsung: endian fixes for IO
Message-ID<rHQyu-3JS-35@gated-at.bofh.it>
In reply to#1417756
From: Ben Dooks <ben.dooks@codethink.co.uk>

Use the relaxed versions of the IO accessors to avoid any issues
if running in big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
Cc: Pavel Fedin <p.fedin@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Pankaj Dubey <pankaj.dubey@samsung.com>
Cc: linux-arm-kernel@lists.codethink.co.uk
---
 drivers/memory/samsung/exynos-srom.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/memory/samsung/exynos-srom.c b/drivers/memory/samsung/exynos-srom.c
index 96756fb..ac8f79c 100644
--- a/drivers/memory/samsung/exynos-srom.c
+++ b/drivers/memory/samsung/exynos-srom.c
@@ -91,11 +91,11 @@ static int exynos_srom_configure_bank(struct exynos_srom *srom,
 	if (width == 2)
 		cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT;
 
-	bw = __raw_readl(srom->reg_base + EXYNOS_SROM_BW);
+	bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW);
 	bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);
-	__raw_writel(bw, srom->reg_base + EXYNOS_SROM_BW);
+	writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
 
-	__raw_writel(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
+	writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
 		    (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
 		    (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
 		    (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
-- 
2.8.3

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#1417762 — [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian
Message-ID<rHQyu-3JS-31@gated-at.bofh.it>
In reply to#1417756
Fix the serial access code to deal with kernels built for big endian
operation.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
---
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Jiri Slaby <jslaby@suse.com>
CC: linux-serial@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
 drivers/tty/serial/samsung.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index fc5deaa..8818bdd 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -118,9 +118,9 @@ struct s3c24xx_uart_port {
 	((unsigned long *)(unsigned long)((port)->membase + (reg)))
 
 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
-#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
+#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 
 #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
-#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
+#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 
 #endif
-- 
2.8.3

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#1418155 — Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian

FromBen Dooks <ben.dooks@codethink.co.uk>
Date2016-06-09 10:20 +0200
SubjectRe: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian
Message-ID<rI3m1-3Lg-1@gated-at.bofh.it>
In reply to#1417762
On 08/06/16 19:31, Matthew Leach wrote:
> Fix the serial access code to deal with kernels built for big endian
> operation.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>
> ---
> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> CC: Jiri Slaby <jslaby@suse.com>
> CC: linux-serial@vger.kernel.org
> CC: linux-kernel@vger.kernel.org
> ---
>  drivers/tty/serial/samsung.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
> index fc5deaa..8818bdd 100644
> --- a/drivers/tty/serial/samsung.h
> +++ b/drivers/tty/serial/samsung.h
> @@ -118,9 +118,9 @@ struct s3c24xx_uart_port {
>  	((unsigned long *)(unsigned long)((port)->membase + (reg)))
>  
>  #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
> -#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
> +#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
>  
>  #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
> -#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
> +#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))

I suppose for complete-ness we should have changed the readbs as well.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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#1419196 — Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian

FromBen Dooks <ben.dooks@codethink.co.uk>
Date2016-06-10 12:20 +0200
SubjectRe: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian
Message-ID<rIrHI-3il-23@gated-at.bofh.it>
In reply to#1417762
On 08/06/16 19:31, Matthew Leach wrote:
> Fix the serial access code to deal with kernels built for big endian
> operation.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>
> ---
> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> CC: Jiri Slaby <jslaby@suse.com>
> CC: linux-serial@vger.kernel.org
> CC: linux-kernel@vger.kernel.org
> ---
>  drivers/tty/serial/samsung.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
> index fc5deaa..8818bdd 100644
> --- a/drivers/tty/serial/samsung.h
> +++ b/drivers/tty/serial/samsung.h
> @@ -118,9 +118,9 @@ struct s3c24xx_uart_port {
>  	((unsigned long *)(unsigned long)((port)->membase + (reg)))
>  
>  #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
> -#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
> +#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))

For completeness we should have changed __raw_readb to readb_relaxed

>  #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
> -#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
> +#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))

Acked-by: Ben Dooks <ben.dooks@codethink.co.uk>

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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#1419302 — Re: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-06-10 13:50 +0200
SubjectRe: [RFC PATCH 05/15] tty: serial: samsung: fixup accessors for endian
Message-ID<rIt6N-41N-3@gated-at.bofh.it>
In reply to#1419196
On 06/10/2016 12:13 PM, Ben Dooks wrote:
> On 08/06/16 19:31, Matthew Leach wrote:
>> Fix the serial access code to deal with kernels built for big endian
>> operation.
>>
>> Signed-off-by: Matthew Leach <matthew@mattleach.net>
>> ---
>> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> CC: Jiri Slaby <jslaby@suse.com>
>> CC: linux-serial@vger.kernel.org
>> CC: linux-kernel@vger.kernel.org
>> ---
>>  drivers/tty/serial/samsung.h | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
>> index fc5deaa..8818bdd 100644
>> --- a/drivers/tty/serial/samsung.h
>> +++ b/drivers/tty/serial/samsung.h
>> @@ -118,9 +118,9 @@ struct s3c24xx_uart_port {
>>  	((unsigned long *)(unsigned long)((port)->membase + (reg)))
>>  
>>  #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
>> -#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
>> +#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
> 
> For completeness we should have changed __raw_readb to readb_relaxed
> 
>>  #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
>> -#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
>> +#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
> 
> Acked-by: Ben Dooks <ben.dooks@codethink.co.uk>


With the readb_relaced change:
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

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#1417763 — [RFC PATCH 01/15] clock: exynos: fixup endian in pll clk

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 01/15] clock: exynos: fixup endian in pll clk
Message-ID<rHQyu-3JS-33@gated-at.bofh.it>
In reply to#1417756
Fix the clk endian access code to deal with kernels built for big endian
operation.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
---
CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Tomasz Figa <tomasz.figa@gmail.com>
CC: Michael Turquette <mturquette@baylibre.com>
CC: Stephen Boyd <sboyd@codeaurora.org>
CC: linux-samsung-soc@vger.kernel.org
CC: linux-clk@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
 drivers/clk/samsung/clk-pll.c | 122 +++++++++++++++++++++---------------------
 1 file changed, 61 insertions(+), 61 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b7dd396..48139bd 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -79,7 +79,7 @@ static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
 	u32 pll_con, mdiv, pdiv, sdiv;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
 	pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
 	sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
@@ -112,7 +112,7 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
 	u32 pll_con, mdiv, pdiv, sdiv;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
 	pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
 	sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
@@ -149,7 +149,7 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
 	pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
 	sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -186,19 +186,19 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		return -EINVAL;
 	}
 
-	tmp = __raw_readl(pll->con_reg);
+	tmp = readl_relaxed(pll->con_reg);
 
 	if (!(samsung_pll35xx_mp_change(rate, tmp))) {
 		/* If only s change, change just s value only*/
 		tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
 		tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
-		__raw_writel(tmp, pll->con_reg);
+		writel_relaxed(tmp, pll->con_reg);
 
 		return 0;
 	}
 
 	/* Set PLL lock time. */
-	__raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR,
+	writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
 			pll->lock_reg);
 
 	/* Change PLL PMS values */
@@ -208,12 +208,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
 			(rate->pdiv << PLL35XX_PDIV_SHIFT) |
 			(rate->sdiv << PLL35XX_SDIV_SHIFT);
-	__raw_writel(tmp, pll->con_reg);
+	writel_relaxed(tmp, pll->con_reg);
 
 	/* wait_lock_time */
 	do {
 		cpu_relax();
-		tmp = __raw_readl(pll->con_reg);
+		tmp = readl_relaxed(pll->con_reg);
 	} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
 				<< PLL35XX_LOCK_STAT_SHIFT)));
 	return 0;
@@ -253,8 +253,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 	s16 kdiv;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con1 = __raw_readl(pll->con_reg + 4);
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con1 = readl_relaxed(pll->con_reg + 4);
 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
@@ -294,20 +294,20 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		return -EINVAL;
 	}
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con1 = __raw_readl(pll->con_reg + 4);
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con1 = readl_relaxed(pll->con_reg + 4);
 
 	if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
 		/* If only s change, change just s value only*/
 		pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
 		pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
-		__raw_writel(pll_con0, pll->con_reg);
+		writel_relaxed(pll_con0, pll->con_reg);
 
 		return 0;
 	}
 
 	/* Set PLL lock time. */
-	__raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
+	writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
 
 	 /* Change PLL PMS values */
 	pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
@@ -316,16 +316,16 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
 			(rate->pdiv << PLL36XX_PDIV_SHIFT) |
 			(rate->sdiv << PLL36XX_SDIV_SHIFT);
-	__raw_writel(pll_con0, pll->con_reg);
+	writel_relaxed(pll_con0, pll->con_reg);
 
 	pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
 	pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
-	__raw_writel(pll_con1, pll->con_reg + 4);
+	writel_relaxed(pll_con1, pll->con_reg + 4);
 
 	/* wait_lock_time */
 	do {
 		cpu_relax();
-		tmp = __raw_readl(pll->con_reg);
+		tmp = readl_relaxed(pll->con_reg);
 	} while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
 
 	return 0;
@@ -366,7 +366,7 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
 	pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
 	sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
@@ -409,14 +409,14 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		return -EINVAL;
 	}
 
-	con0 = __raw_readl(pll->con_reg);
-	con1 = __raw_readl(pll->con_reg + 0x4);
+	con0 = readl_relaxed(pll->con_reg);
+	con1 = readl_relaxed(pll->con_reg + 0x4);
 
 	if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
 		/* If only s change, change just s value only*/
 		con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
 		con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
-		__raw_writel(con0, pll->con_reg);
+		writel_relaxed(con0, pll->con_reg);
 
 		return 0;
 	}
@@ -430,29 +430,29 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
 			(rate->sdiv << PLL45XX_SDIV_SHIFT);
 
 	/* Set PLL AFC value. */
-	con1 = __raw_readl(pll->con_reg + 0x4);
+	con1 = readl_relaxed(pll->con_reg + 0x4);
 	con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
 	con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
 
 	/* Set PLL lock time. */
 	switch (pll->type) {
 	case pll_4502:
-		__raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
+		writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
 		break;
 	case pll_4508:
-		__raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
+		writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
 		break;
 	default:
 		break;
 	}
 
 	/* Set new configuration. */
-	__raw_writel(con1, pll->con_reg + 0x4);
-	__raw_writel(con0, pll->con_reg);
+	writel_relaxed(con1, pll->con_reg + 0x4);
+	writel_relaxed(con0, pll->con_reg);
 
 	/* Wait for locking. */
 	start = ktime_get();
-	while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) {
+	while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) {
 		ktime_t delta = ktime_sub(ktime_get(), start);
 
 		if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -513,8 +513,8 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con1 = __raw_readl(pll->con_reg + 4);
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con1 = readl_relaxed(pll->con_reg + 4);
 	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
 				PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
 	pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
@@ -560,14 +560,14 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		return -EINVAL;
 	}
 
-	con0 = __raw_readl(pll->con_reg);
-	con1 = __raw_readl(pll->con_reg + 0x4);
+	con0 = readl_relaxed(pll->con_reg);
+	con1 = readl_relaxed(pll->con_reg + 0x4);
 
 	if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
 		/* If only s change, change just s value only*/
 		con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
 		con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
-		__raw_writel(con0, pll->con_reg);
+		writel_relaxed(con0, pll->con_reg);
 
 		return 0;
 	}
@@ -596,7 +596,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 			(rate->sdiv << PLL46XX_SDIV_SHIFT);
 
 	/* Set PLL K, MFR and MRR values. */
-	con1 = __raw_readl(pll->con_reg + 0x4);
+	con1 = readl_relaxed(pll->con_reg + 0x4);
 	con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
 			(PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
 			(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
@@ -605,13 +605,13 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 			(rate->mrr << PLL46XX_MRR_SHIFT);
 
 	/* Write configuration to PLL */
-	__raw_writel(lock, pll->lock_reg);
-	__raw_writel(con0, pll->con_reg);
-	__raw_writel(con1, pll->con_reg + 0x4);
+	writel_relaxed(lock, pll->lock_reg);
+	writel_relaxed(con0, pll->con_reg);
+	writel_relaxed(con1, pll->con_reg + 0x4);
 
 	/* Wait for locking. */
 	start = ktime_get();
-	while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) {
+	while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) {
 		ktime_t delta = ktime_sub(ktime_get(), start);
 
 		if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -656,7 +656,7 @@ static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	if (pll->type == pll_6552_s3c2416) {
 		mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
 		pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
@@ -696,8 +696,8 @@ static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con1 = __raw_readl(pll->con_reg + 0x4);
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con1 = readl_relaxed(pll->con_reg + 0x4);
 	mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
@@ -734,7 +734,7 @@ static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw,
 	u32 pll_con, mdiv, pdiv, sdiv;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
 	pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
 	sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
@@ -752,7 +752,7 @@ static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw,
 	u32 pll_con, mdiv, pdiv, sdiv;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
 	pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
 	sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
@@ -778,7 +778,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 		return -EINVAL;
 	}
 
-	tmp = __raw_readl(pll->con_reg);
+	tmp = readl_relaxed(pll->con_reg);
 
 	/* Change PLL PMS values */
 	tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) |
@@ -787,7 +787,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 	tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) |
 			(rate->pdiv << PLLS3C2410_PDIV_SHIFT) |
 			(rate->sdiv << PLLS3C2410_SDIV_SHIFT);
-	__raw_writel(tmp, pll->con_reg);
+	writel_relaxed(tmp, pll->con_reg);
 
 	/* Time to settle according to the manual */
 	udelay(300);
@@ -798,7 +798,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
 {
 	struct samsung_clk_pll *pll = to_clk_pll(hw);
-	u32 pll_en = __raw_readl(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
+	u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
 	u32 pll_en_orig = pll_en;
 
 	if (enable)
@@ -806,7 +806,7 @@ static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
 	else
 		pll_en |= BIT(bit);
 
-	__raw_writel(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
+	writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
 
 	/* if we started the UPLL, then allow to settle */
 	if (enable && (pll_en_orig & BIT(bit)))
@@ -905,7 +905,7 @@ static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
 	u32 r, p, m, s, pll_stat;
 	u64 fvco = parent_rate;
 
-	pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
+	pll_stat = readl_relaxed(pll->reg_base + pll->offset * 3);
 	r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
 	if (!r)
 		return 0;
@@ -983,7 +983,7 @@ static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
 	u32 mdiv, pdiv, sdiv, pll_con;
 	u64 fvco = parent_rate;
 
-	pll_con = __raw_readl(pll->con_reg);
+	pll_con = readl_relaxed(pll->con_reg);
 	mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
 	pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
 	sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
@@ -1019,19 +1019,19 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		return -EINVAL;
 	}
 
-	tmp = __raw_readl(pll->con_reg);
+	tmp = readl_relaxed(pll->con_reg);
 
 	if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
 		/* If only s change, change just s value only*/
 		tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
 		tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
-		__raw_writel(tmp, pll->con_reg);
+		writel_relaxed(tmp, pll->con_reg);
 
 		return 0;
 	}
 
 	/* Set PLL lock time. */
-	__raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
+	writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
 
 	/* Change PLL PMS values */
 	tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
@@ -1040,12 +1040,12 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
 			(rate->pdiv << PLL2550XX_P_SHIFT) |
 			(rate->sdiv << PLL2550XX_S_SHIFT);
-	__raw_writel(tmp, pll->con_reg);
+	writel_relaxed(tmp, pll->con_reg);
 
 	/* wait_lock_time */
 	do {
 		cpu_relax();
-		tmp = __raw_readl(pll->con_reg);
+		tmp = readl_relaxed(pll->con_reg);
 	} while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
 			<< PLL2550XX_LOCK_STAT_SHIFT)));
 
@@ -1089,8 +1089,8 @@ static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
 	s16 kdiv;
 	u64 fvco = parent_rate;
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con2 = __raw_readl(pll->con_reg + 8);
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con2 = readl_relaxed(pll->con_reg + 8);
 	mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
@@ -1117,8 +1117,8 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		return -EINVAL;
 	}
 
-	pll_con0 = __raw_readl(pll->con_reg);
-	pll_con2 = __raw_readl(pll->con_reg + 8);
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con2 = readl_relaxed(pll->con_reg + 8);
 
 	 /* Change PLL PMS values */
 	pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
@@ -1135,13 +1135,13 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
 			<< PLL2650XX_KDIV_SHIFT;
 
 	/* Set PLL lock time. */
-	__raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+	writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
 
-	__raw_writel(pll_con0, pll->con_reg);
-	__raw_writel(pll_con2, pll->con_reg + 8);
+	writel_relaxed(pll_con0, pll->con_reg);
+	writel_relaxed(pll_con2, pll->con_reg + 8);
 
 	do {
-		tmp = __raw_readl(pll->con_reg);
+		tmp = readl_relaxed(pll->con_reg);
 	} while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
 
 	return 0;
-- 
2.8.3

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#1419181 — Re: [RFC PATCH 01/15] clock: exynos: fixup endian in pll clk

FromSylwester Nawrocki <s.nawrocki@samsung.com>
Date2016-06-10 12:00 +0200
SubjectRe: [RFC PATCH 01/15] clock: exynos: fixup endian in pll clk
Message-ID<rIrol-2W0-7@gated-at.bofh.it>
In reply to#1417763
On 06/08/2016 08:30 PM, Matthew Leach wrote:
> Fix the clk endian access code to deal with kernels built for big endian
> operation.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>

We should have gotten rid of those __raw_{readl, writel} calls earlier
for other reasons too. Thanks for the fix, patch applied!

-- 
Regards,
Sylwester

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#1417764 — [RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit functions

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit functions
Message-ID<rHQyu-3JS-41@gated-at.bofh.it>
In reply to#1417756
This driver makes use of the __set_bit() and __clear_bit() functions.
When running under big-endian, these functions don't convert the bit
indexes when working with peripheral registers, leading to the
incorrect bits being set and cleared when running big-endian.

Add two new driver functions for setting and clearing bits that are
byte-order aware.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
---
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Jiri Slaby <jslaby@suse.com>
CC: linux-serial@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
 drivers/tty/serial/samsung.c | 16 +++++++---------
 drivers/tty/serial/samsung.h | 29 +++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 9 deletions(-)

diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 99bb231..e4f53d5 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -169,8 +169,7 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port)
 		return;
 
 	if (s3c24xx_serial_has_interrupt_mask(port))
-		__set_bit(S3C64XX_UINTM_TXD,
-			portaddrl(port, S3C64XX_UINTM));
+		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 	else
 		disable_irq_nosync(ourport->tx_irq);
 
@@ -235,8 +234,7 @@ static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 
 	/* Mask Tx interrupt */
 	if (s3c24xx_serial_has_interrupt_mask(port))
-		__set_bit(S3C64XX_UINTM_TXD,
-			  portaddrl(port, S3C64XX_UINTM));
+		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 	else
 		disable_irq_nosync(ourport->tx_irq);
 
@@ -269,8 +267,8 @@ static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 
 	/* Unmask Tx interrupt */
 	if (s3c24xx_serial_has_interrupt_mask(port))
-		__clear_bit(S3C64XX_UINTM_TXD,
-			    portaddrl(port, S3C64XX_UINTM));
+		s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
+				  S3C64XX_UINTM);
 	else
 		enable_irq(ourport->tx_irq);
 
@@ -397,8 +395,8 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port)
 	if (rx_enabled(port)) {
 		dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 		if (s3c24xx_serial_has_interrupt_mask(port))
-			__set_bit(S3C64XX_UINTM_RXD,
-				portaddrl(port, S3C64XX_UINTM));
+			s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
+					S3C64XX_UINTM);
 		else
 			disable_irq_nosync(ourport->rx_irq);
 		rx_enabled(port) = 0;
@@ -1069,7 +1067,7 @@ static int s3c64xx_serial_startup(struct uart_port *port)
 	spin_unlock_irqrestore(&port->lock, flags);
 
 	/* Enable Rx Interrupt */
-	__clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
+	s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
 
 	dbg("s3c64xx_serial_startup ok\n");
 	return ret;
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 8818bdd..e45745a 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -111,6 +111,7 @@ struct s3c24xx_uart_port {
 
 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 
+
 /* register access controls */
 
 #define portaddr(port, reg) ((port)->membase + (reg))
@@ -123,4 +124,32 @@ struct s3c24xx_uart_port {
 #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 
+/* Byte-order aware bit setting/clearing functions. */
+
+static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
+				   unsigned int reg)
+{
+	unsigned long flags;
+	u32 val;
+
+	local_irq_save(flags);
+	val = rd_regl(port, reg);
+	val |= (1 << idx);
+	wr_regl(port, reg, val);
+	local_irq_restore(flags);
+}
+
+static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
+				     unsigned int reg)
+{
+	unsigned long flags;
+	u32 val;
+
+	local_irq_save(flags);
+	val = rd_regl(port, reg);
+	val &= ~(1 << idx);
+	wr_regl(port, reg, val);
+	local_irq_restore(flags);
+}
+
 #endif
-- 
2.8.3

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#1419321 — Re: [RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit functions

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-06-10 14:20 +0200
SubjectRe: [RFC PATCH 06/15] tty: serial: samsung: add byte-order aware bit functions
Message-ID<rItzP-4sE-1@gated-at.bofh.it>
In reply to#1417764
On 06/08/2016 08:31 PM, Matthew Leach wrote:
> This driver makes use of the __set_bit() and __clear_bit() functions.
> When running under big-endian, these functions don't convert the bit
> indexes when working with peripheral registers, leading to the
> incorrect bits being set and cleared when running big-endian.
> 
> Add two new driver functions for setting and clearing bits that are
> byte-order aware.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>
> ---
> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> CC: Jiri Slaby <jslaby@suse.com>
> CC: linux-serial@vger.kernel.org
> CC: linux-kernel@vger.kernel.org
> ---
>  drivers/tty/serial/samsung.c | 16 +++++++---------
>  drivers/tty/serial/samsung.h | 29 +++++++++++++++++++++++++++++
>  2 files changed, 36 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
> index 99bb231..e4f53d5 100644
> --- a/drivers/tty/serial/samsung.c
> +++ b/drivers/tty/serial/samsung.c
> @@ -169,8 +169,7 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port)
>  		return;
>  
>  	if (s3c24xx_serial_has_interrupt_mask(port))
> -		__set_bit(S3C64XX_UINTM_TXD,
> -			portaddrl(port, S3C64XX_UINTM));
> +		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
>  	else
>  		disable_irq_nosync(ourport->tx_irq);
>  
> @@ -235,8 +234,7 @@ static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
>  
>  	/* Mask Tx interrupt */
>  	if (s3c24xx_serial_has_interrupt_mask(port))
> -		__set_bit(S3C64XX_UINTM_TXD,
> -			  portaddrl(port, S3C64XX_UINTM));
> +		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
>  	else
>  		disable_irq_nosync(ourport->tx_irq);
>  
> @@ -269,8 +267,8 @@ static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
>  
>  	/* Unmask Tx interrupt */
>  	if (s3c24xx_serial_has_interrupt_mask(port))
> -		__clear_bit(S3C64XX_UINTM_TXD,
> -			    portaddrl(port, S3C64XX_UINTM));
> +		s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
> +				  S3C64XX_UINTM);
>  	else
>  		enable_irq(ourport->tx_irq);
>  
> @@ -397,8 +395,8 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port)
>  	if (rx_enabled(port)) {
>  		dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
>  		if (s3c24xx_serial_has_interrupt_mask(port))
> -			__set_bit(S3C64XX_UINTM_RXD,
> -				portaddrl(port, S3C64XX_UINTM));
> +			s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
> +					S3C64XX_UINTM);
>  		else
>  			disable_irq_nosync(ourport->rx_irq);
>  		rx_enabled(port) = 0;
> @@ -1069,7 +1067,7 @@ static int s3c64xx_serial_startup(struct uart_port *port)
>  	spin_unlock_irqrestore(&port->lock, flags);
>  
>  	/* Enable Rx Interrupt */
> -	__clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
> +	s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
>  
>  	dbg("s3c64xx_serial_startup ok\n");
>  	return ret;
> diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
> index 8818bdd..e45745a 100644
> --- a/drivers/tty/serial/samsung.h
> +++ b/drivers/tty/serial/samsung.h
> @@ -111,6 +111,7 @@ struct s3c24xx_uart_port {
>  
>  #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
>  
> +

This new line looks unnecessary. Beside that it looks okay:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

>  /* register access controls */
>  
>  #define portaddr(port, reg) ((port)->membase + (reg))
> @@ -123,4 +124,32 @@ struct s3c24xx_uart_port {
>  #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
>  #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
>  
> +/* Byte-order aware bit setting/clearing functions. */
> +
> +static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
> +				   unsigned int reg)
> +{
> +	unsigned long flags;
> +	u32 val;
> +
> +	local_irq_save(flags);
> +	val = rd_regl(port, reg);
> +	val |= (1 << idx);
> +	wr_regl(port, reg, val);
> +	local_irq_restore(flags);
> +}
> +
> +static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
> +				     unsigned int reg)
> +{
> +	unsigned long flags;
> +	u32 val;
> +
> +	local_irq_save(flags);
> +	val = rd_regl(port, reg);
> +	val &= ~(1 << idx);
> +	wr_regl(port, reg, val);
> +	local_irq_restore(flags);
> +}
> +
>  #endif
>

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#1417765 — [RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be
Message-ID<rHQyu-3JS-43@gated-at.bofh.it>
In reply to#1417756
Use the byte-order aware big endian accessors, allowing for kernels
running under big-endian.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
---
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Jason Cooper <jason@lakedaemon.net>
CC: Marc Zyngier <marc.zyngier@arm.com>
CC: Kukjin Kim <kgene@kernel.org>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-samsung-soc@vger.kernel.org
---
 drivers/irqchip/exynos-combiner.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index ead15be..b78a169 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
 {
 	u32 mask = 1 << (data->hwirq % 32);
 
-	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
 	u32 mask = 1 << (data->hwirq % 32);
 
-	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
 
 static void combiner_handle_cascade_irq(struct irq_desc *desc)
@@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 
 	spin_lock(&irq_controller_lock);
-	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+	status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
 	spin_unlock(&irq_controller_lock);
 	status &= chip_data->irq_mask;
 
@@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
 	combiner_data->parent_irq = irq;
 
 	/* Disable all interrupts */
-	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
+	writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
 }
 
 static int combiner_irq_domain_xlate(struct irq_domain *d,
@@ -218,7 +218,7 @@ static int combiner_suspend(void)
 
 	for (i = 0; i < max_nr; i++)
 		combiner_data[i].pm_save =
-			__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
+			readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
 
 	return 0;
 }
@@ -235,9 +235,9 @@ static void combiner_resume(void)
 	int i;
 
 	for (i = 0; i < max_nr; i++) {
-		__raw_writel(combiner_data[i].irq_mask,
+		writel_relaxed(combiner_data[i].irq_mask,
 			     combiner_data[i].base + COMBINER_ENABLE_CLEAR);
-		__raw_writel(combiner_data[i].pm_save,
+		writel_relaxed(combiner_data[i].pm_save,
 			     combiner_data[i].base + COMBINER_ENABLE_SET);
 	}
 }
-- 
2.8.3

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#1419300 — Re: [RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-06-10 13:50 +0200
SubjectRe: [RFC PATCH 04/15] irqchip: exynos_combiner: fixup reg access on be
Message-ID<rIt6N-41N-1@gated-at.bofh.it>
In reply to#1417765
On 06/08/2016 08:30 PM, Matthew Leach wrote:
> Use the byte-order aware big endian accessors, allowing for kernels
> running under big-endian.
> 
> Signed-off-by: Matthew Leach <matthew@mattleach.net>
> ---
> CC: Thomas Gleixner <tglx@linutronix.de>
> CC: Jason Cooper <jason@lakedaemon.net>
> CC: Marc Zyngier <marc.zyngier@arm.com>
> CC: Kukjin Kim <kgene@kernel.org>
> CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> CC: linux-kernel@vger.kernel.org
> CC: linux-arm-kernel@lists.infradead.org
> CC: linux-samsung-soc@vger.kernel.org
> ---
>  drivers/irqchip/exynos-combiner.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
> index ead15be..b78a169 100644
> --- a/drivers/irqchip/exynos-combiner.c
> +++ b/drivers/irqchip/exynos-combiner.c
> @@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
>  {
>  	u32 mask = 1 << (data->hwirq % 32);
>  
> -	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
> +	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
>  }
>  
>  static void combiner_unmask_irq(struct irq_data *data)
>  {
>  	u32 mask = 1 << (data->hwirq % 32);
>  
> -	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
> +	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
>  }
>  
>  static void combiner_handle_cascade_irq(struct irq_desc *desc)
> @@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
>  	chained_irq_enter(chip, desc);
>  
>  	spin_lock(&irq_controller_lock);
> -	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
> +	status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
>  	spin_unlock(&irq_controller_lock);
>  	status &= chip_data->irq_mask;
>  
> @@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
>  	combiner_data->parent_irq = irq;
>  
>  	/* Disable all interrupts */
> -	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
> +	writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
>  }
>  
>  static int combiner_irq_domain_xlate(struct irq_domain *d,
> @@ -218,7 +218,7 @@ static int combiner_suspend(void)
>  
>  	for (i = 0; i < max_nr; i++)
>  		combiner_data[i].pm_save =
> -			__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
> +			readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
>  
>  	return 0;
>  }
> @@ -235,9 +235,9 @@ static void combiner_resume(void)
>  	int i;
>  
>  	for (i = 0; i < max_nr; i++) {
> -		__raw_writel(combiner_data[i].irq_mask,
> +		writel_relaxed(combiner_data[i].irq_mask,
>  			     combiner_data[i].base + COMBINER_ENABLE_CLEAR);
> -		__raw_writel(combiner_data[i].pm_save,
> +		writel_relaxed(combiner_data[i].pm_save,
>  			     combiner_data[i].base + COMBINER_ENABLE_SET);

Indentation of arguments is broken. I think it was aligned before.

Beside that:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

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#1417766 — [RFC PATCH 10/15] ARM: EXYNOS: fixup endian in pm/pmu

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 10/15] ARM: EXYNOS: fixup endian in pm/pmu
Message-ID<rHQyu-3JS-53@gated-at.bofh.it>
In reply to#1417756
From: Ben Dooks <ben.dooks@codethink.co.uk>

Fix the PMU code endian access code to deal with kernels built for big endian
operation.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/mach-exynos/common.h     | 4 ++--
 arch/arm/mach-exynos/pm.c         | 4 ++--
 arch/arm/mach-exynos/pm_domains.c | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 5365bf1..19e9d25 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -174,12 +174,12 @@ extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
 
 static inline void pmu_raw_writel(u32 val, u32 offset)
 {
-	__raw_writel(val, pmu_base_addr + offset);
+	writel_relaxed(val, pmu_base_addr + offset);
 }
 
 static inline u32 pmu_raw_readl(u32 offset)
 {
-	return __raw_readl(pmu_base_addr + offset);
+	return readl_relaxed(pmu_base_addr + offset);
 }
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c43b776..52d78eb 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -132,9 +132,9 @@ static void exynos_set_wakeupmask(long mask)
 
 static void exynos_cpu_set_boot_vector(long flags)
 {
-	__raw_writel(virt_to_phys(exynos_cpu_resume),
+	writel_relaxed(virt_to_phys(exynos_cpu_resume),
 		     exynos_boot_vector_addr());
-	__raw_writel(flags, exynos_boot_vector_flag());
+	writel_relaxed(flags, exynos_boot_vector_flag());
 }
 
 static int exynos_aftr_finisher(unsigned long flags)
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 875a2ba..0e075d9 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -70,12 +70,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 	}
 
 	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
-	__raw_writel(pwr, base);
+	writel_relaxed(pwr, base);
 
 	/* Wait max 1ms */
 	timeout = 10;
 
-	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
+	while ((readl_relaxed(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
 		if (!timeout) {
 			op = (power_on) ? "enable" : "disable";
 			pr_err("Power domain %s %s failed\n", domain->name, op);
@@ -185,7 +185,7 @@ static __init int exynos4_pm_init_power_domain(void)
 			clk_put(pd->oscclk);
 
 no_clk:
-		on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
+		on = readl_relaxed(pd->base + 0x4) & INT_LOCAL_PWR_EN;
 
 		pm_genpd_init(&pd->pd, NULL, !on);
 		of_genpd_add_provider_simple(np, &pd->pd);
-- 
2.8.3

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#1417767 — [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian

FromMatthew Leach <matthew@mattleach.net>
Date2016-06-08 20:40 +0200
Subject[RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian
Message-ID<rHQyv-3JS-67@gated-at.bofh.it>
In reply to#1417756
From: Ben Dooks <ben.dooks@codethink.co.uk>

The exynos low-level debug macros need to be fixed if the system is being
built big endian. Add the necessary endian swaps for accessing the registers
to get output working again

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/include/debug/samsung.S | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index 8d8d922..f4eeed2 100644
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -15,11 +15,13 @@
 
 	.macro fifo_level_s5pv210 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		and	\rd, \rd, #S5PV210_UFSTAT_TXMASK
 	.endm
 
 	.macro  fifo_full_s5pv210 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S5PV210_UFSTAT_TXFULL
 	.endm
 
@@ -28,6 +30,7 @@
 
 	.macro fifo_level_s3c2440 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		and	\rd, \rd, #S3C2440_UFSTAT_TXMASK
 	.endm
 
@@ -37,6 +40,7 @@
 
 	.macro  fifo_full_s3c2440 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2440_UFSTAT_TXFULL
 	.endm
 
@@ -50,6 +54,7 @@
 
 	.macro	busyuart, rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFCON]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
 		beq	1001f				@
 		@ FIFO enabled...
@@ -61,6 +66,7 @@
 1001:
 		@ busy waiting for non fifo
 		ldr	\rd, [\rx, # S3C2410_UTRSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UTRSTAT_TXFE
 		beq	1001b
 
@@ -69,6 +75,7 @@
 
 	.macro	waituart,rd,rx
 		ldr	\rd, [\rx, # S3C2410_UFCON]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
 		beq	1001f				@
 		@ FIFO enabled...
@@ -80,6 +87,7 @@
 1001:
 		@ idle waiting for non fifo
 		ldr	\rd, [\rx, # S3C2410_UTRSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UTRSTAT_TXFE
 		beq	1001b
 
-- 
2.8.3

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#1419273 — Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-06-10 13:20 +0200
SubjectRe: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian
Message-ID<rIsDL-3RQ-11@gated-at.bofh.it>
In reply to#1417767
On 06/10/2016 01:12 PM, Ben Dooks wrote:
> On 08/06/16 19:31, Matthew Leach wrote:
>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>
>> The exynos low-level debug macros need to be fixed if the system is being
>> built big endian. Add the necessary endian swaps for accessing the registers
>> to get output working again
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> ---
>>  arch/arm/include/debug/samsung.S | 8 ++++++++
>>  1 file changed, 8 insertions(+)
> 
> Should this go via the maintainer or to RMK?
> 
> If to RMK, then shall I get it submitted (and does anyone else
> want to ack?)

If there are no objections, I can take it through samsung-soc with other
arch/arm/mach-exynos* patches.

What I am missing here, is Matthew's Signed-off-by.

Matthew, you touched and sent the patch so could you add the Sob?

Best regards,
Krzysztof

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#1419351 — Re: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian

FromBen Dooks <ben.dooks@codethink.co.uk>
Date2016-06-10 14:50 +0200
SubjectRe: [RFC PATCH 07/15] ARM: exynos: fixup debug macros for big-endian
Message-ID<rIu2R-4CJ-1@gated-at.bofh.it>
In reply to#1419273
On 10/06/16 12:16, Krzysztof Kozlowski wrote:
> On 06/10/2016 01:12 PM, Ben Dooks wrote:
>> On 08/06/16 19:31, Matthew Leach wrote:
>>> From: Ben Dooks <ben.dooks@codethink.co.uk>
>>>
>>> The exynos low-level debug macros need to be fixed if the system is being
>>> built big endian. Add the necessary endian swaps for accessing the registers
>>> to get output working again
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> ---
>>>  arch/arm/include/debug/samsung.S | 8 ++++++++
>>>  1 file changed, 8 insertions(+)
>>
>> Should this go via the maintainer or to RMK?
>>
>> If to RMK, then shall I get it submitted (and does anyone else
>> want to ack?)
> 
> If there are no objections, I can take it through samsung-soc with other
> arch/arm/mach-exynos* patches.
> 
> What I am missing here, is Matthew's Signed-off-by.
> 
> Matthew, you touched and sent the patch so could you add the Sob?

Either that or I could just send it from my tree directly.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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