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[PATCH v2 00/11] iommu/ipmmu-vmsa: r8a7795 support V2

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  [PATCH v2 00/11] iommu/ipmmu-vmsa: r8a7795 support V2 Magnus Damm <magnus.damm@gmail.com> - 2016-06-06 06:10 +0200
    [PATCH v2 08/11] iommu/ipmmu-vmsa: Write IMCTR twice Magnus Damm <magnus.damm@gmail.com> - 2016-06-06 06:20 +0200
    [PATCH v2 07/11] iommu/ipmmu-vmsa: IPMMU device is 64-bit bus master Magnus Damm <magnus.damm@gmail.com> - 2016-06-06 06:20 +0200
    Re: [PATCH v2 00/11] iommu/ipmmu-vmsa: r8a7795 support V2 Geert Uytterhoeven <geert@linux-m68k.org> - 2016-06-06 09:10 +0200

#1414612 — [PATCH v2 00/11] iommu/ipmmu-vmsa: r8a7795 support V2

iommu/ipmmu-vmsa: r8a7795 support V2

[PATCH v2 01/11] iommu/ipmmu-vmsa: Introduce features, break out alias
[PATCH v2 02/11] iommu/ipmmu-vmsa: Add optional root device feature
[PATCH v2 03/11] iommu/ipmmu-vmsa: Enable multi context support
[PATCH v2 04/11] iommu/ipmmu-vmsa: Reuse iommu groups
[PATCH v2 05/11] iommu/ipmmu-vmsa: Make use of IOMMU_OF_DECLARE()
[PATCH v2 06/11] iommu/ipmmu-vmsa: Teach xlate() to skip disabled iommus
[PATCH v2 07/11] iommu/ipmmu-vmsa: IPMMU device is 64-bit bus master
[PATCH v2 08/11] iommu/ipmmu-vmsa: Write IMCTR twice
[PATCH v2 09/11] iommu/ipmmu-vmsa: Make IMBUSCTR setup optional
[PATCH v2 10/11] iommu/ipmmu-vmsa: Allow two bit SL0
[PATCH v2 11/11] iommu/ipmmu-vmsa: Hook up r8a7795 DT matching code

This series contains updated r8a7795 support for the IPMMU driver
compared to the earlier series posted as:

[PATCH 00/10] iommu/ipmmu-vmsa: Initial r8a7795 support

The DT binding for r8a7795 has been accepted for upstream merge
and this series implements support following such format:

d4e42e7 iommu/ipmmu-vmsa: Add r8a7795 DT binding

The r8a7795 IPMMU is almost register compatible with earlier devices
like r8a7790-r8a7794, however some bitfields have been shifted
slightly. On a grander scale topology has been added and interrupts
have been reworked. So now there are several "cache" IPMMU units
without interrupt that somehow communicate with IPMMU-MM that
is the only instance that supports interrupts. The code refers to
IPMMU-MM as a "root" device and the other ones as leaf nodes.

To make this more interesting the IPMMU driver needs to be shared
between 32-bit ARM for r8a7790-r8a7794 and 64-bit ARM for r8a7795.
In practice this means that two separate implementations are needed
inside the driver to attach to the rather different architecture
specific code.

CONFIG_IOMMU_DMA=y is needed on 64-bit ARM while on 32-bit ARM
the arch specific dma-mapping code is hooked up rather directly.
During init 64-bit ARM IPMMU support is relying on IOMMU_OF_DECLARE().

This version of the code is known to build on 32-bit and 64-bit ARM.

Compared to V1 the patches have been reordered and multi context
and iommu group code has been reworked. Now devices are grouped
together based on the IPMMU they are connected to. For detail
please see the change log in each individual patch.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Developed on top of next-20160602 and:
 [PATCH v3 00/06] iommu/ipmmu-vmsa: IPMMU multi-arch update V3

 drivers/iommu/ipmmu-vmsa.c |  318 +++++++++++++++++++++++++++++++++++++-------
 1 file changed, 269 insertions(+), 49 deletions(-)

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#1414613 — [PATCH v2 08/11] iommu/ipmmu-vmsa: Write IMCTR twice

From: Magnus Damm <damm+renesas@opensource.se>

Write IMCTR both in the root device and the leaf node.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Changes since V1:
 - None

 drivers/iommu/ipmmu-vmsa.c |   17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

--- 0021/drivers/iommu/ipmmu-vmsa.c
+++ work/drivers/iommu/ipmmu-vmsa.c	2016-06-06 11:03:22.610607110 +0900
@@ -261,6 +261,16 @@ static void ipmmu_ctx_write(struct ipmmu
 	ipmmu_write(domain->root, domain->context_id * IM_CTX_SIZE + reg, data);
 }
 
+static void ipmmu_ctx_write2(struct ipmmu_vmsa_domain *domain, unsigned int reg,
+			     u32 data)
+{
+	if (domain->mmu != domain->root)
+		ipmmu_write(domain->mmu,
+			    domain->context_id * IM_CTX_SIZE + reg, data);
+
+	ipmmu_write(domain->root, domain->context_id * IM_CTX_SIZE + reg, data);
+}
+
 /* -----------------------------------------------------------------------------
  * TLB and microTLB Management
  */
@@ -287,7 +297,7 @@ static void ipmmu_tlb_invalidate(struct
 
 	reg = ipmmu_ctx_read(domain, IMCTR);
 	reg |= IMCTR_FLUSH;
-	ipmmu_ctx_write(domain, IMCTR, reg);
+	ipmmu_ctx_write2(domain, IMCTR, reg);
 
 	ipmmu_tlb_sync(domain);
 }
@@ -445,7 +455,8 @@ static int ipmmu_domain_init_context(str
 	 * software management as we have no use for it. Flush the TLB as
 	 * required when modifying the context registers.
 	 */
-	ipmmu_ctx_write(domain, IMCTR, IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
+	ipmmu_ctx_write2(domain, IMCTR,
+			 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
 
 	return 0;
 }
@@ -471,7 +482,7 @@ static void ipmmu_domain_destroy_context
 	 *
 	 * TODO: Is TLB flush really needed ?
 	 */
-	ipmmu_ctx_write(domain, IMCTR, IMCTR_FLUSH);
+	ipmmu_ctx_write2(domain, IMCTR, IMCTR_FLUSH);
 	ipmmu_tlb_sync(domain);
 	ipmmu_domain_free_context(domain->root, domain->context_id);
 }

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#1414615 — [PATCH v2 07/11] iommu/ipmmu-vmsa: IPMMU device is 64-bit bus master

From: Magnus Damm <damm+renesas@opensource.se>

The r8a7795 IPMMU supports 64-bit bus mastering. Both
the coherent DMA mask and the streaming DMA mask are
set to unlock the 64-bit address space for coherent
allocations and streaming operations.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Changes since V1:
 - Updated the commit message

 drivers/iommu/ipmmu-vmsa.c |    1 +
 1 file changed, 1 insertion(+)

--- 0019/drivers/iommu/ipmmu-vmsa.c
+++ work/drivers/iommu/ipmmu-vmsa.c	2016-06-06 11:01:28.730607110 +0900
@@ -1082,6 +1082,7 @@ static int ipmmu_probe(struct platform_d
 	spin_lock_init(&mmu->lock);
 	bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
 	mmu->features = match->data;
+	dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 
 	/* Map I/O memory and request IRQ. */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

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#1414690

Hi Magnus,

On Mon, Jun 6, 2016 at 5:57 AM, Magnus Damm <magnus.damm@gmail.com> wrote:
> iommu/ipmmu-vmsa: r8a7795 support V2
>
> [PATCH v2 01/11] iommu/ipmmu-vmsa: Introduce features, break out alias
> [PATCH v2 02/11] iommu/ipmmu-vmsa: Add optional root device feature
> [PATCH v2 03/11] iommu/ipmmu-vmsa: Enable multi context support
> [PATCH v2 04/11] iommu/ipmmu-vmsa: Reuse iommu groups
> [PATCH v2 05/11] iommu/ipmmu-vmsa: Make use of IOMMU_OF_DECLARE()
> [PATCH v2 06/11] iommu/ipmmu-vmsa: Teach xlate() to skip disabled iommus
> [PATCH v2 07/11] iommu/ipmmu-vmsa: IPMMU device is 64-bit bus master
> [PATCH v2 08/11] iommu/ipmmu-vmsa: Write IMCTR twice
> [PATCH v2 09/11] iommu/ipmmu-vmsa: Make IMBUSCTR setup optional
> [PATCH v2 10/11] iommu/ipmmu-vmsa: Allow two bit SL0
> [PATCH v2 11/11] iommu/ipmmu-vmsa: Hook up r8a7795 DT matching code

Thanks for your series!

For your convenience, I've queued it up in topic/r8a7795-ipmmu-v2 at
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git, and
will include it in next renesas-drivers release.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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