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[PATCH 0/4] ASoC: sunxi: Add i2s controller support

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  [PATCH 0/4] ASoC: sunxi: Add i2s controller support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-06-01 20:00 +0200
    [PATCH 3/4] ARM: sun7i: Add mod1 clock nodes Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-06-01 20:00 +0200

#1411433 — [PATCH 0/4] ASoC: sunxi: Add i2s controller support

Hi everyone,

This is the first version of the I2S support for the controller found
in the Allwinner A10 and later SoCs.

Playback has been tested with an UDA1380 on an A20-Olinuxino. Capture
is not implemented yet, but will come eventually.

Let me know what you think,
Maxime

Emilio López (1):
  ARM: sun7i: Add mod1 clock nodes

Maxime Ripard (3):
  dt-bindings: Add A10 I2S controller binding documentation
  ASoC: sunxi: Add Allwinner A10 Digital Audio driver
  ARM: sun7i: Add DAI nodes

 .../devicetree/bindings/sound/sun4i-i2s.txt        |  33 +
 arch/arm/boot/dts/sun7i-a20.dtsi                   |  87 ++-
 sound/soc/sunxi/Kconfig                            |  10 +
 sound/soc/sunxi/Makefile                           |   2 +-
 sound/soc/sunxi/sun4i-i2s.c                        | 714 +++++++++++++++++++++
 5 files changed, 843 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/sun4i-i2s.txt
 create mode 100644 sound/soc/sunxi/sun4i-i2s.c

-- 
2.8.3

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#1411436 — [PATCH 3/4] ARM: sun7i: Add mod1 clock nodes

From: Emilio López <emilio@elopez.com.ar>

This commit adds all the mod1 clocks available on A20 to its device
tree. This list was created by looking at the A20 user manual.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 48 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index febdf4c72fb0..603fda5b7f94 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -366,9 +366,9 @@
 					<5>, <6>, <7>,
 					<8>, <10>;
 			clock-output-names = "apb0_codec", "apb0_spdif",
-				"apb0_ac97", "apb0_iis0", "apb0_iis1",
+				"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 				"apb0_pio", "apb0_ir0", "apb0_ir1",
-				"apb0_iis2", "apb0_keypad";
+				"apb0_i2s2", "apb0_keypad";
 		};
 
 		apb1: clk@01c20058 {
@@ -518,6 +518,28 @@
 			clock-output-names = "ir1";
 		};
 
+		i2s0_clk: clk@01c200b8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200b8 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "i2s0";
+		};
+
+		ac97_clk: clk@01c200bc {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200bc 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "ac97";
+		};
+
 		spdif_clk: clk@01c200c0 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod1-clk";
@@ -555,6 +577,28 @@
 			clock-output-names = "spi3";
 		};
 
+		i2s1_clk: clk@01c200d8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200d8 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "i2s1";
+		};
+
+		i2s2_clk: clk@01c200dc {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200dc 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "i2s2";
+		};
+
 		dram_gates: clk@01c20100 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-dram-gates-clk";
-- 
2.8.3

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