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Re: [PATCH] tty: serial: msm: Disable restoring Rx interrupts for DMA Mode

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  Re: [PATCH] tty: serial: msm: Disable restoring Rx interrupts for DMA  Mode charanya@codeaurora.org - 2016-06-02 11:10 +0200
    Re: [PATCH] tty: serial: msm: Disable restoring Rx interrupts for  DMA Mode Stephen Boyd <sboyd@codeaurora.org> - 2016-06-02 20:40 +0200

#1412017 — Re: [PATCH] tty: serial: msm: Disable restoring Rx interrupts for DMA Mode

On 2016-05-26 04:16, Stephen Boyd wrote:
> On 05/13, charanya@codeaurora.org wrote:
>> Hi Stephen/Andy,
>> 
>> If both Tx and Rx are used simultaneously, restoring Rx interrupts in
>> msm_complete_rx_dma could lead to RXSTALE interrupt being triggered,
>> when
>> the ISR execution for TXLEV interrupt is completed, since
>> msm_port->imr is
>> rewritten to UART_IMR in msm_uart_irq. Hence, we do not have to 
>> restore
>> Rx interrupts since Rx is always in DMA mode once enabled.
>> 
> 
> Ok, but what's the exact sequence of events that happens? I think
> we unlock the spinlock in the dma completion handler and then the
> txlev interrupt runs? At that point we may have more data to push
> out and then rx stale handling runs and corrupts the fifo state?
> 
> I was hoping for some sort of CPU sequence of events like:
> 
>  CPU0                   CPU1
>  ----                   ----
> 
>  msm_start_rx_dma()
>                        msm_complete_rx_dma()
> 		        spin_unlock_irqrestore(&port->lock)
>  msm_uart_irq()
>   msm_handle_rx_dm()
>    <Read from FIFO and breaks>
> 
> This patch seems correct, but the commit text isn't fully
> describing the sequence of events that causes this to happen, so
> it's taking a while to convince myself that this patch fixes
> anything.


The sequence of events is as mentioned. When the TXLEV interrupt occurs 
after the
spinlock is unlocked, the rx stale handling runs since the interrupts 
are restored
and hence it corrupts the fifo state.

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#1412494 — Re: [PATCH] tty: serial: msm: Disable restoring Rx interrupts for DMA Mode

On 06/02, charanya@codeaurora.org wrote:
> On 2016-05-26 04:16, Stephen Boyd wrote:
> >
> >Ok, but what's the exact sequence of events that happens? I think
> >we unlock the spinlock in the dma completion handler and then the
> >txlev interrupt runs? At that point we may have more data to push
> >out and then rx stale handling runs and corrupts the fifo state?
> >
> >I was hoping for some sort of CPU sequence of events like:
> >
> > CPU0                   CPU1
> > ----                   ----
> >
> > msm_start_rx_dma()
> >                       msm_complete_rx_dma()
> >		        spin_unlock_irqrestore(&port->lock)
> > msm_uart_irq()
> >  msm_handle_rx_dm()
> >   <Read from FIFO and breaks>
> >
> >This patch seems correct, but the commit text isn't fully
> >describing the sequence of events that causes this to happen, so
> >it's taking a while to convince myself that this patch fixes
> >anything.
> 
> 
> The sequence of events is as mentioned. When the TXLEV interrupt
> occurs after the
> spinlock is unlocked, the rx stale handling runs since the
> interrupts are restored
> and hence it corrupts the fifo state.

Ok, care to put such information into the commit text of the
patch and resend then please? It will help us later to recall
what the actual problem was.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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