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[PATCH 0/5] Patches for QCOM IPQ4019 clock driver

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  [PATCH 0/5] Patches for QCOM IPQ4019 clock driver Abhishek Sahu <absahu@codeaurora.org> - 2016-05-30 16:40 +0200
    [PATCH 4/5] clk: qcom: ipq4019: Added the cpu clock frequency change notifier Abhishek Sahu <absahu@codeaurora.org> - 2016-05-30 16:40 +0200
    [PATCH 3/5] clk: qcom: ipq4019: Added the cpu pll divider and changed regmap limit Abhishek Sahu <absahu@codeaurora.org> - 2016-05-30 16:40 +0200

#1409172 — [PATCH 0/5] Patches for QCOM IPQ4019 clock driver

These patches are related to Qualcomm IPQ4019 GCC (Global Clock
Controller) driver code mainly adding support for multiple CPU
frequencies and corrected fixed clock values.

Abhishek Sahu (5):
  clk: qcom: ipq4019: Modified the fixed clock rate to proper values
  clk: qcom: ipq4019: Added the apss cpu pll divider clock node
  clk: qcom: ipq4019: Added the cpu pll divider and changed regmap limit
  clk: qcom: ipq4019: Added the cpu clock frequency change notifier
  clk: qcom: ipq4019: Added the turbo frequency for apps cpu

 drivers/clk/qcom/gcc-ipq4019.c               | 195 +++++++++++++++++++++++++--
 include/dt-bindings/clock/qcom,gcc-ipq4019.h |   1 +
 2 files changed, 183 insertions(+), 13 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1409174 — [PATCH 4/5] clk: qcom: ipq4019: Added the cpu clock frequency change notifier

The current IPQ4019 clock driver code gives the crash or gets hang
while switching the CPU frequency some time. The APSS CPU Clock
divider is not glitch free so the APPS clock need to be switched for
stable clock duringthe change.

This patch adds the frequency change notifier for APSS CPU clock.
It changes the parent of this clock to stable PLL FEPLL500 when it
gets for PRE_RATE_CHANGE event. This event will be generated before
actual clock set operations. The clock set operation will again change
its corresponding parent by getting the same from frequency table.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 263577c..69a8250 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1455,9 +1455,27 @@ static const struct of_device_id gcc_ipq4019_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
 
+int cpu_clk_notifier_fn(struct notifier_block *nb,
+			unsigned long action, void *data)
+{
+	int err = 0;
+
+	if (action == PRE_RATE_CHANGE) {
+		err = clk_rcg2_ops.set_parent(&apps_clk_src.clkr.hw,
+							P_FEPLL500);
+	}
+
+	return notifier_from_errno(err);
+}
+
+struct notifier_block cpu_clk_notifier = {
+	.notifier_call = cpu_clk_notifier_fn,
+};
+
 static int gcc_ipq4019_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	int err;
 
 	clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000);
 	clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000);
@@ -1469,7 +1487,13 @@ static int gcc_ipq4019_probe(struct platform_device *pdev)
 	clk_register_fixed_rate(dev, "ddrpllsdcc", "xo", 0, 193000000);
 	clk_register_fixed_rate(dev, "pcnoc_clk_src", "xo", 0, 100000000);
 
-	return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
+	err = qcom_cc_probe(pdev, &gcc_ipq4019_desc);
+
+	if (!err)
+		clk_notifier_register(apps_clk_src.clkr.hw.clk,
+					&cpu_clk_notifier);
+
+	return err;
 }
 
 static struct platform_driver gcc_ipq4019_driver = {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1409177 — [PATCH 3/5] clk: qcom: ipq4019: Added the cpu pll divider and changed regmap limit

This patch adds the APSS CPU PLL divider in clock framework and
its binding in IPQ4019 device tree binding.

Also, it changed the max_register value to 0x2FFFF in regmap config
to support the APSS CPU PLL divider operations.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq4019.c               | 6 ++++--
 include/dt-bindings/clock/qcom,gcc-ipq4019.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 45f4749..263577c 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -143,7 +143,7 @@ static const char * const gcc_xo_ddr_500_200[] = {
 	"xo",
 	"fepll200",
 	"fepll500",
-	"ddrpllapss",
+	"gcc_apps_cpu_div_clk",
 };
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -682,6 +682,7 @@ static struct clk_rcg2 apps_clk_src = {
 		.parent_names = gcc_xo_ddr_500_200,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -1355,6 +1356,7 @@ static struct clk_regmap *gcc_ipq4019_clocks[] = {
 	[GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
 	[GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
 	[GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
+	[GCC_APPS_CLK_CPU_DIV] = &gcc_apps_cpu_div_clk.cdiv.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
@@ -1435,7 +1437,7 @@ static const struct regmap_config gcc_ipq4019_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
-	.max_register	= 0x2dfff,
+	.max_register	= 0x2FFFF,
 	.fast_io	= true,
 };
 
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
index 6240e5b..417a722 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -154,5 +154,6 @@
 #define GCC_QDSS_BCR					69
 #define GCC_MPM_BCR					70
 #define GCC_SPDM_BCR					71
+#define GCC_APPS_CLK_CPU_DIV				72
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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