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[PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()

Started byPeter Zijlstra <peterz@infradead.org>
First post2016-05-31 12:40 +0200
Last post2016-06-01 10:50 +0200
Articles 4 — 2 participants

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  [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}() Peter Zijlstra <peterz@infradead.org> - 2016-05-31 12:40 +0200
    Re: [PATCH -v2 19/33] locking,powerpc: Implement  atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}() Boqun Feng <boqun.feng@gmail.com> - 2016-06-01 05:10 +0200
      Re: [PATCH -v2 19/33] locking,powerpc: Implement  atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}() Boqun Feng <boqun.feng@gmail.com> - 2016-06-01 08:10 +0200
        Re: [PATCH -v2 19/33] locking,powerpc: Implement  atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}() Peter Zijlstra <peterz@infradead.org> - 2016-06-01 10:50 +0200

#1410106 — [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()

FromPeter Zijlstra <peterz@infradead.org>
Date2016-05-31 12:40 +0200
Subject[PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()
Message-ID<rEPfA-1vx-57@gated-at.bofh.it>
Implement FETCH-OP atomic primitives, these are very similar to the
existing OP-RETURN primitives we already have, except they return the
value of the atomic variable _before_ modification.

This is especially useful for irreversible operations -- such as
bitops (because it becomes impossible to reconstruct the state prior
to modification).

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
 arch/powerpc/include/asm/atomic.h |   83 +++++++++++++++++++++++++++++++++-----
 1 file changed, 74 insertions(+), 9 deletions(-)

--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -78,21 +78,53 @@ static inline int atomic_##op##_return_r
 	return t;							\
 }
 
+#define ATOMIC_FETCH_OP_RELAXED(op, asm_op)				\
+static inline int atomic_fetch_##op##_relaxed(int a, atomic_t *v)	\
+{									\
+	int res, t;							\
+									\
+	__asm__ __volatile__(						\
+"1:	lwarx	%0,0,%4		# atomic_fetch_" #op "_relaxed\n"	\
+	#asm_op " %1,%3,%0\n"						\
+	PPC405_ERR77(0, %4)						\
+"	stwcx.	%1,0,%4\n"						\
+"	bne-	1b\n"							\
+	: "=&r" (res), "=&r" (t), "+m" (v->counter)			\
+	: "r" (a), "r" (&v->counter)					\
+	: "cc");							\
+									\
+	return res;							\
+}
+
 #define ATOMIC_OPS(op, asm_op)						\
 	ATOMIC_OP(op, asm_op)						\
-	ATOMIC_OP_RETURN_RELAXED(op, asm_op)
+	ATOMIC_OP_RETURN_RELAXED(op, asm_op)				\
+	ATOMIC_FETCH_OP_RELAXED(op, asm_op)
 
 ATOMIC_OPS(add, add)
 ATOMIC_OPS(sub, subf)
 
-ATOMIC_OP(and, and)
-ATOMIC_OP(or, or)
-ATOMIC_OP(xor, xor)
-
 #define atomic_add_return_relaxed atomic_add_return_relaxed
 #define atomic_sub_return_relaxed atomic_sub_return_relaxed
 
+#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
+#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
+
+#undef ATOMIC_OPS
+#define ATOMIC_OPS(op, asm_op)						\
+	ATOMIC_OP(op, asm_op)						\
+	ATOMIC_FETCH_OP_RELAXED(op, asm_op)
+
+ATOMIC_OPS(and, and)
+ATOMIC_OPS(or, or)
+ATOMIC_OPS(xor, xor)
+
+#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
+#define atomic_fetch_or_relaxed  atomic_fetch_or_relaxed
+#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
+
 #undef ATOMIC_OPS
+#undef ATOMIC_FETCH_OP_RELAXED
 #undef ATOMIC_OP_RETURN_RELAXED
 #undef ATOMIC_OP
 
@@ -329,20 +361,53 @@ atomic64_##op##_return_relaxed(long a, a
 	return t;							\
 }
 
+#define ATOMIC64_FETCH_OP_RELAXED(op, asm_op)				\
+static inline long							\
+atomic64_fetch_##op##_relaxed(long a, atomic64_t *v)			\
+{									\
+	long res, t;							\
+									\
+	__asm__ __volatile__(						\
+"1:	ldarx	%0,0,%4		# atomic64_fetch_" #op "_relaxed\n"	\
+	#asm_op " %1,%3,%0\n"						\
+"	stdcx.	%1,0,%4\n"						\
+"	bne-	1b\n"							\
+	: "=&r" (res), "=&r" (t), "+m" (v->counter)			\
+	: "r" (a), "r" (&v->counter)					\
+	: "cc");							\
+									\
+	return t;							\
+}
+
 #define ATOMIC64_OPS(op, asm_op)					\
 	ATOMIC64_OP(op, asm_op)						\
-	ATOMIC64_OP_RETURN_RELAXED(op, asm_op)
+	ATOMIC64_OP_RETURN_RELAXED(op, asm_op)				\
+	ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
 
 ATOMIC64_OPS(add, add)
 ATOMIC64_OPS(sub, subf)
-ATOMIC64_OP(and, and)
-ATOMIC64_OP(or, or)
-ATOMIC64_OP(xor, xor)
 
 #define atomic64_add_return_relaxed atomic64_add_return_relaxed
 #define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
 
+#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
+#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
+
+#undef ATOMIC64_OPS
+#define ATOMIC64_OPS(op, asm_op)					\
+	ATOMIC64_OP(op, asm_op)						\
+	ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
+
+ATOMIC64_OPS(and, and)
+ATOMIC64_OPS(or, or)
+ATOMIC64_OPS(xor, xor)
+
+#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
+#define atomic64_fetch_or_relaxed  atomic64_fetch_or_relaxed
+#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
+
 #undef ATOPIC64_OPS
+#undef ATOMIC64_FETCH_OP_RELAXED
 #undef ATOMIC64_OP_RETURN_RELAXED
 #undef ATOMIC64_OP

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#1410794 — Re: [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()

FromBoqun Feng <boqun.feng@gmail.com>
Date2016-06-01 05:10 +0200
SubjectRe: [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()
Message-ID<rF4HE-2SZ-9@gated-at.bofh.it>
In reply to#1410106

[Multipart message — attachments visible in raw view] — view raw

Hi Peter,

On Tue, May 31, 2016 at 12:19:44PM +0200, Peter Zijlstra wrote:
[snip]
>  
> @@ -329,20 +361,53 @@ atomic64_##op##_return_relaxed(long a, a
>  	return t;							\
>  }
>  
> +#define ATOMIC64_FETCH_OP_RELAXED(op, asm_op)				\
> +static inline long							\
> +atomic64_fetch_##op##_relaxed(long a, atomic64_t *v)			\
> +{									\
> +	long res, t;							\
> +									\
> +	__asm__ __volatile__(						\
> +"1:	ldarx	%0,0,%4		# atomic64_fetch_" #op "_relaxed\n"	\
> +	#asm_op " %1,%3,%0\n"						\
> +"	stdcx.	%1,0,%4\n"						\
> +"	bne-	1b\n"							\
> +	: "=&r" (res), "=&r" (t), "+m" (v->counter)			\
> +	: "r" (a), "r" (&v->counter)					\
> +	: "cc");							\
> +									\
> +	return t;							\

Looks like I missed this one in v1, it should be
	
	return res;

because the primitives will return the values before modified by the
operations.

Regards,
Boqun

> +}
> +

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#1410835 — Re: [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()

FromBoqun Feng <boqun.feng@gmail.com>
Date2016-06-01 08:10 +0200
SubjectRe: [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()
Message-ID<rF7vP-4JC-3@gated-at.bofh.it>
In reply to#1410794

[Multipart message — attachments visible in raw view] — view raw

On Wed, Jun 01, 2016 at 11:11:38AM +0800, Boqun Feng wrote:
> Hi Peter,
> 
> On Tue, May 31, 2016 at 12:19:44PM +0200, Peter Zijlstra wrote:
> [snip]
> >  
> > @@ -329,20 +361,53 @@ atomic64_##op##_return_relaxed(long a, a
> >  	return t;							\
> >  }
> >  
> > +#define ATOMIC64_FETCH_OP_RELAXED(op, asm_op)				\
> > +static inline long							\
> > +atomic64_fetch_##op##_relaxed(long a, atomic64_t *v)			\
> > +{									\
> > +	long res, t;							\
> > +									\
> > +	__asm__ __volatile__(						\
> > +"1:	ldarx	%0,0,%4		# atomic64_fetch_" #op "_relaxed\n"	\
> > +	#asm_op " %1,%3,%0\n"						\
> > +"	stdcx.	%1,0,%4\n"						\
> > +"	bne-	1b\n"							\
> > +	: "=&r" (res), "=&r" (t), "+m" (v->counter)			\
> > +	: "r" (a), "r" (&v->counter)					\
> > +	: "cc");							\
> > +									\
> > +	return t;							\
> 
> Looks like I missed this one in v1, it should be
> 	
> 	return res;
> 
> because the primitives will return the values before modified by the
> operations.
> 

FWIW, I tested on ppc with ATOMIC64_SELFTEST=y for the following branch:

git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git locking/atomic (afee54ef5b1f2b04)

without this modification, I can hit:

------------[ cut here ]------------
kernel BUG at lib/atomic64_test.c:181!
Oops: Exception in kernel mode, sig: 5 [#1]

with this modification, all the atomic selftests are passed ;-)

Regards,
Boqun

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#1410968 — Re: [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()

FromPeter Zijlstra <peterz@infradead.org>
Date2016-06-01 10:50 +0200
SubjectRe: [PATCH -v2 19/33] locking,powerpc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}{,_relaxed,_acquire,_release}()
Message-ID<rFa0G-67A-13@gated-at.bofh.it>
In reply to#1410835
On Wed, Jun 01, 2016 at 02:10:45PM +0800, Boqun Feng wrote:
> On Wed, Jun 01, 2016 at 11:11:38AM +0800, Boqun Feng wrote:

> > Looks like I missed this one in v1, it should be
> > 	
> > 	return res;

Indeed.

> > because the primitives will return the values before modified by the
> > operations.
> > 
> 
> FWIW, I tested on ppc with ATOMIC64_SELFTEST=y for the following branch:

Thanks, I'll add a tested-by tag with your name on ;-)

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