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Groups > linux.kernel > #1408414 > unrolled thread

[PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid XU

Started byKrzysztof Kozlowski <krzk@kernel.org>
First post2016-05-28 12:00 +0200
Last post2016-05-31 11:20 +0200
Articles 8 on this page of 28 — 6 participants

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  [PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid XU Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 18/22] dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 13/22] ARM: dts: exynos: Enable UART3 on Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
      Re: [PATCH v5 13/22] ARM: dts: exynos: Enable UART3 on Exynos5410 Kevin Hilman <khilman@kernel.org> - 2016-06-01 22:00 +0200
        Re: [PATCH v5 13/22] ARM: dts: exynos: Enable UART3 on Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-06-01 22:10 +0200
          Re: [PATCH v5 13/22] ARM: dts: exynos: Enable UART3 on Exynos5410 Javier Martinez Canillas <javier@osg.samsung.com> - 2016-06-01 23:00 +0200
            Re: [PATCH v5 13/22] ARM: dts: exynos: Enable UART3 on Exynos5410 Javier Martinez Canillas <javier@osg.samsung.com> - 2016-06-01 23:00 +0200
              Re: [PATCH v5 13/22] ARM: dts: exynos: Enable UART3 on Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-06-02 06:20 +0200
    [PATCH v5 12/22] ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 20/22] ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 07/22] ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 21/22] ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 10/22] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 16/22] ARM: dts: exynos: Add USB to Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 05/22] ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 02/22] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 22/22] ARM: dts: exynos: Add RTC and I2C to Exynos5410 Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 15/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 01/22] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 14/22] ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 19/22] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
      Re: [PATCH v5 19/22] clk: samsung: exynos5410: Add I2C, HSI2C and  RTC clocks Stephen Boyd <sboyd@codeaurora.org> - 2016-06-02 00:20 +0200
    [PATCH v5 03/22] clk: samsung: exynos5410: Add serial3, USB and PWM clocks Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 17/22] ARM: dts: exynos: Add initial support for Odroid XU board Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:00 +0200
    [PATCH v5 06/22] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:10 +0200
    [PATCH v5 04/22] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes Krzysztof Kozlowski <krzk@kernel.org> - 2016-05-28 12:10 +0200
    Re: [PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid  XU Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-05-30 17:30 +0200
      Re: [PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid  XU Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-05-31 11:20 +0200

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#1408432 — [PATCH v5 19/22] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks

FromKrzysztof Kozlowski <krzk@kernel.org>
Date2016-05-28 12:00 +0200
Subject[PATCH v5 19/22] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks
Message-ID<rDJck-7iX-53@gated-at.bofh.it>
In reply to#1408414
Add clocks for I2C, USI (HSI2C) and RTC to the Exynos5410 clock driver.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
 drivers/clk/samsung/clk-exynos5410.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index 5f892128849a..6c2e59c576ee 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -159,6 +159,7 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
 
 static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 	GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+	GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
 
 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
 			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
@@ -187,6 +188,14 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 	GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
 	GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
 	GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
+	GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
+	GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
+	GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
+	GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
+	GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
+	GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
+	GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
+	GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
 	GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
 
 	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
-- 
2.7.4

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#1411621 — Re: [PATCH v5 19/22] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks

FromStephen Boyd <sboyd@codeaurora.org>
Date2016-06-02 00:20 +0200
SubjectRe: [PATCH v5 19/22] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks
Message-ID<rFmEx-63v-9@gated-at.bofh.it>
In reply to#1408432
On 05/28, Krzysztof Kozlowski wrote:
> Add clocks for I2C, USI (HSI2C) and RTC to the Exynos5410 clock driver.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1408433 — [PATCH v5 03/22] clk: samsung: exynos5410: Add serial3, USB and PWM clocks

FromKrzysztof Kozlowski <krzk@kernel.org>
Date2016-05-28 12:00 +0200
Subject[PATCH v5 03/22] clk: samsung: exynos5410: Add serial3, USB and PWM clocks
Message-ID<rDJcj-7iX-49@gated-at.bofh.it>
In reply to#1408414
Just like other Exynos5 family SoCs, this one has four UARTs. Add
missing UART3 clocks to the Exynos5410 clock driver.

Add clocks for USB and PWM.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
 drivers/clk/samsung/clk-exynos5410.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d5d5dcabc4a9..5f892128849a 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -33,9 +33,11 @@
 #define SRC_CPERI1		0x4204
 #define DIV_TOP0		0x10510
 #define DIV_TOP1		0x10514
+#define DIV_FSYS0		0x10548
 #define DIV_FSYS1		0x1054c
 #define DIV_FSYS2		0x10550
 #define DIV_PERIC0		0x10558
+#define DIV_PERIC3		0x10564
 #define SRC_TOP0		0x10210
 #define SRC_TOP1		0x10214
 #define SRC_TOP2		0x10218
@@ -44,6 +46,8 @@
 #define SRC_MASK_FSYS		0x10340
 #define SRC_MASK_PERIC0		0x10350
 #define GATE_BUS_FSYS0		0x10740
+#define GATE_TOP_SCLK_FSYS	0x10840
+#define GATE_TOP_SCLK_PERIC	0x10850
 #define GATE_IP_FSYS		0x10944
 #define GATE_IP_PERIC		0x10950
 #define GATE_IP_PERIS		0x10960
@@ -71,6 +75,7 @@ PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
 PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
 PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
 PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+PNAME(sclk_mpll_bpll_p)	= { "sclk_mpll_bpll", "fin_pll", };
 
 PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
 			"none", "none", "sclk_mpll_bpll",
@@ -96,10 +101,14 @@ static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
 	MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
 	MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
 	MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+	MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
+	MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
 
 	MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
 	MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
 	MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+	MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
+	MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
 
 	MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
 	MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
@@ -121,6 +130,11 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
 	DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
 	DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
 
+	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
+	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
+
 	DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 	DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
 	DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
@@ -137,6 +151,8 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
 	DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
 	DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
 
+	DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
+
 	DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
 	DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
 };
@@ -155,9 +171,23 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 	GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
 	GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
 
+	GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
+	     GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
+	     GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
+	     GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
+	     GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
+	     GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+
 	GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
 	GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
 	GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+	GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
+	GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
 
 	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
 			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
@@ -165,6 +195,12 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
 			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+			SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
 };
 
 static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
-- 
2.7.4

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#1408434 — [PATCH v5 17/22] ARM: dts: exynos: Add initial support for Odroid XU board

FromKrzysztof Kozlowski <krzk@kernel.org>
Date2016-05-28 12:00 +0200
Subject[PATCH v5 17/22] ARM: dts: exynos: Add initial support for Odroid XU board
Message-ID<rDJck-7iX-63@gated-at.bofh.it>
In reply to#1408414
The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
from Samsung: the Exynos5410. Details:
1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is
   enabled),
2. 2 GB DDR3 RAM,
3. PowerVR SGX544MP3 GPU (not enabled in DTS),
4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4,
5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of
   revisions though),
6. eMMC 4.5 and microSD slots.

Comparing this board to Odroid XU3 (more popular), the differences are:
1. Exynos5410 instead of 5422,
2. MIPI DSI LCD connector,
3. Main PMIC: Maxim 77802 instead of S2MPS11,
4. USB3503+LAN9730 instead of integrated LAN9514,
5. eMMC 4.5 instead of eMMC 5.0,

This patch adds initial support for the XU board with working basic
functions, eMMC/SD and USB (including attached ethernet adapter).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Link: http://www.hardkernel.com/main/products/prdt_info.php?g_code=G137510300620
---
 .../bindings/arm/samsung/samsung-boards.txt        |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/exynos5410-odroidxu.dts          | 121 +++++++++++++++++++++
 3 files changed, 123 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos5410-odroidxu.dts

diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index f5deace2b380..0ea7f14ef294 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -47,6 +47,7 @@ Required root node properties:
 	- "hardkernel,odroid-u3"  - for Exynos4412-based Hardkernel Odroid U3.
 	- "hardkernel,odroid-x"   - for Exynos4412-based Hardkernel Odroid X.
 	- "hardkernel,odroid-x2"  - for Exynos4412-based Hardkernel Odroid X2.
+	- "hardkernel,odroid-xu"  - for Exynos5410-based Hardkernel Odroid XU.
 	- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
 	- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
 					 Odroid XU3 Lite board.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5aeb10674370..9ed1c7abedb1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
 	exynos5250-snow-rev5.dtb \
 	exynos5250-spring.dtb \
 	exynos5260-xyref5260.dtb \
+	exynos5410-odroidxu.dtb \
 	exynos5410-smdk5410.dtb \
 	exynos5420-arndale-octa.dtb \
 	exynos5420-peach-pit.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
new file mode 100644
index 000000000000..9fe04500ecaf
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -0,0 +1,121 @@
+/*
+ * Hardkernel Odroid XU board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "exynos54xx-odroidxu-leds.dtsi"
+
+/ {
+	model = "Hardkernel Odroid XU";
+	compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
+
+	memory {
+		reg = <0x40000000 0x7ea00000>;
+	};
+
+	chosen {
+		linux,stdout-path = &serial_2;
+	};
+
+	emmc_pwrseq: pwrseq {
+		pinctrl-0 = <&emmc_nrst_pin>;
+		pinctrl-names = "default";
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
+	};
+
+	fan0: pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm 0 20972 0>;
+		cooling-min-state = <0>;
+		cooling-max-state = <3>;
+		#cooling-cells = <2>;
+		cooling-levels = <0 130 170 230>;
+	};
+
+	fin_pll: xxti {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "fin_pll";
+		#clock-cells = <0>;
+	};
+
+	firmware@02073000 {
+		compatible = "samsung,secure-firmware";
+		reg = <0x02073000 0x1000>;
+	};
+};
+
+&mmc_0 {
+	status = "okay";
+	mmc-pwrseq = <&emmc_pwrseq>;
+	cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	samsung,dw-mshc-hs400-timing = <0 2>;
+	samsung,read-strobe-delay = <90>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+};
+
+&mmc_2 {
+	status = "okay";
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+};
+
+&pinctrl_0 {
+	emmc_nrst_pin: emmc-nrst {
+		samsung,pins = "gpd1-0";
+		samsung,pin-function = <0>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <0>;
+	};
+};
+
+&serial_0 {
+	status = "okay";
+};
+
+&serial_1 {
+	status = "okay";
+};
+
+&serial_2 {
+	status = "okay";
+};
+
+&serial_3 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "peripheral";
+};
-- 
2.7.4

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#1408435 — [PATCH v5 06/22] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card

FromKrzysztof Kozlowski <krzk@kernel.org>
Date2016-05-28 12:10 +0200
Subject[PATCH v5 06/22] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card
Message-ID<rDJlT-7Bi-1@gated-at.bofh.it>
In reply to#1408414
Configure the pinctrl for MMC0 (eMMC) and MMC2 (microSD card).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

---

Important changes since v2:
1. Re-order the eMMC pins by pin-name, not by label.
---
 arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 77 +++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
index f9aa6bb55464..ddacafa1e907 100644
--- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
@@ -277,6 +277,83 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
+
+	sd0_clk: sd0-clk {
+		samsung,pins = "gpc0-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_cmd: sd0-cmd {
+		samsung,pins = "gpc0-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_cd: sd0-cd {
+		samsung,pins = "gpc0-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus1: sd0-bus-width1 {
+		samsung,pins = "gpc0-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus4: sd0-bus-width4 {
+		samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_clk: sd2-clk {
+		samsung,pins = "gpc2-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_cmd: sd2-cmd {
+		samsung,pins = "gpc2-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_cd: sd2-cd {
+		samsung,pins = "gpc2-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_bus1: sd2-bus-width1 {
+		samsung,pins = "gpc2-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_bus4: sd2-bus-width4 {
+		samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus8: sd0-bus-width8 {
+		samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
 };
 
 &pinctrl_1 {
-- 
2.7.4

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#1408436 — [PATCH v5 04/22] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes

FromKrzysztof Kozlowski <krzk@kernel.org>
Date2016-05-28 12:10 +0200
Subject[PATCH v5 04/22] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes
Message-ID<rDJlT-7Bi-9@gated-at.bofh.it>
In reply to#1408414
The 'sd0_rclk' was put in the middle of SD1 nodes. Remove the confusion.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
 arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index 130563b2ca95..14beb7e07323 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -193,17 +193,17 @@
 		samsung,pin-drv = <3>;
 	};
 
-	sd1_clk: sd1-clk {
-		samsung,pins = "gpc1-0";
+	sd0_rclk: sd0-rclk {
+		samsung,pins = "gpc0-7";
 		samsung,pin-function = <2>;
-		samsung,pin-pud = <0>;
+		samsung,pin-pud = <1>;
 		samsung,pin-drv = <3>;
 	};
 
-	sd0_rclk: sd0-rclk {
-		samsung,pins = "gpc0-7";
+	sd1_clk: sd1-clk {
+		samsung,pins = "gpc1-0";
 		samsung,pin-function = <2>;
-		samsung,pin-pud = <1>;
+		samsung,pin-pud = <0>;
 		samsung,pin-drv = <3>;
 	};
 
-- 
2.7.4

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#1409232 — Re: [PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid XU

FromSylwester Nawrocki <s.nawrocki@samsung.com>
Date2016-05-30 17:30 +0200
SubjectRe: [PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid XU
Message-ID<rExiG-5ZF-27@gated-at.bofh.it>
In reply to#1408414
On 05/28/2016 11:54 AM, Krzysztof Kozlowski wrote:
>
> The clock changes can go to clock tree. ARM changes to samsung-soc tree.
> Please provide me a tag with include/dt-bindings/clock commits so I can
> merge it.

I applied the clock tree patches and here is the tag for the three
include/dt-bindings patches:

The following changes since commit 1a695a905c18548062509178b98bc91e67510864:

  Linux 4.7-rc1 (2016-05-29 09:29:24 -0700)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.8-exynos5410-dt

for you to fetch changes up to ed1e1505db0c116affdfab01e650c44a9c459c65:

  dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410
(2016-05-30 16:00:11 +0200)

----------------------------------------------------------------
Adition of missing clock index definitions for exynos5410 SoC
PWM, USB, I2C, and RTC device related clocks.

----------------------------------------------------------------
Krzysztof Kozlowski (3):
      dt-bindings: clock: Add license and reformat Exynos5410 clock IDs
      dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410
      dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410

 include/dt-bindings/clock/exynos5410.h | 73
+++++++++++++++++++++++++++++++++++++++++++++++++++----------------------
 1 file changed, 51 insertions(+), 22 deletions(-)


--
Thanks,
Sylwester

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#1410024 — Re: [PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid XU

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-05-31 11:20 +0200
SubjectRe: [PATCH v5 00/22] ARM: dts: exynos: Add initial support for Odroid XU
Message-ID<rEO0a-NP-23@gated-at.bofh.it>
In reply to#1409232
On 05/30/2016 05:27 PM, Sylwester Nawrocki wrote:
> On 05/28/2016 11:54 AM, Krzysztof Kozlowski wrote:
>>
>> The clock changes can go to clock tree. ARM changes to samsung-soc tree.
>> Please provide me a tag with include/dt-bindings/clock commits so I can
>> merge it.
> 
> I applied the clock tree patches and here is the tag for the three
> include/dt-bindings patches:

Thanks mate!
Pulled.

Best regards,
Krzysztof

> 
> The following changes since commit 1a695a905c18548062509178b98bc91e67510864:
> 
>   Linux 4.7-rc1 (2016-05-29 09:29:24 -0700)
> 
> are available in the git repository at:
> 
>   git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.8-exynos5410-dt
> 
> for you to fetch changes up to ed1e1505db0c116affdfab01e650c44a9c459c65:
> 
>   dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410
> (2016-05-30 16:00:11 +0200)
> 
> ----------------------------------------------------------------
> Adition of missing clock index definitions for exynos5410 SoC
> PWM, USB, I2C, and RTC device related clocks.
> 
> ----------------------------------------------------------------
> Krzysztof Kozlowski (3):
>       dt-bindings: clock: Add license and reformat Exynos5410 clock IDs
>       dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410
>       dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410
> 
>  include/dt-bindings/clock/exynos5410.h | 73
> +++++++++++++++++++++++++++++++++++++++++++++++++++----------------------
>  1 file changed, 51 insertions(+), 22 deletions(-)
> 
> 
> --
> Thanks,
> Sylwester
>

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