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Groups > linux.kernel > #1406169 > unrolled thread
| Started by | Laxman Dewangan <ldewangan@nvidia.com> |
|---|---|
| First post | 2016-05-24 15:30 +0200 |
| Last post | 2016-05-30 17:10 +0200 |
| Articles | 5 — 2 participants |
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[PATCH 1/3] gpio: max77620: Configure interrupt trigger level Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-24 15:30 +0200
[PATCH 2/3] gpio: max77620: Implement gpio_get_direction callback Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-24 15:30 +0200
Re: [PATCH 2/3] gpio: max77620: Implement gpio_get_direction callback Linus Walleij <linus.walleij@linaro.org> - 2016-05-30 17:10 +0200
Re: [PATCH 2/3] gpio: max77620: Implement gpio_get_direction callback Laxman Dewangan <ldewangan@nvidia.com> - 2016-05-31 08:10 +0200
Re: [PATCH 1/3] gpio: max77620: Configure interrupt trigger level Linus Walleij <linus.walleij@linaro.org> - 2016-05-30 17:10 +0200
| From | Laxman Dewangan <ldewangan@nvidia.com> |
|---|---|
| Date | 2016-05-24 15:30 +0200 |
| Subject | [PATCH 1/3] gpio: max77620: Configure interrupt trigger level |
| Message-ID | <rCkzg-3M3-31@gated-at.bofh.it> |
The GPIO sub modules of MAX77620 offers to configure the GPIO
interrupt trigger level as RISING and FALLING edge.
Pass this information to regmap-irg when registering for GPIO
interrupts.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
drivers/gpio/gpio-max77620.c | 67 ++++++++++++++++++++++++++++++++++++++------
1 file changed, 59 insertions(+), 8 deletions(-)
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
index d927562..35f365c 100644
--- a/drivers/gpio/gpio-max77620.c
+++ b/drivers/gpio/gpio-max77620.c
@@ -27,14 +27,62 @@ struct max77620_gpio {
};
static const struct regmap_irq max77620_gpio_irqs[] = {
- REGMAP_IRQ_REG(0, 0, MAX77620_IRQ_LVL2_GPIO_EDGE0),
- REGMAP_IRQ_REG(1, 0, MAX77620_IRQ_LVL2_GPIO_EDGE1),
- REGMAP_IRQ_REG(2, 0, MAX77620_IRQ_LVL2_GPIO_EDGE2),
- REGMAP_IRQ_REG(3, 0, MAX77620_IRQ_LVL2_GPIO_EDGE3),
- REGMAP_IRQ_REG(4, 0, MAX77620_IRQ_LVL2_GPIO_EDGE4),
- REGMAP_IRQ_REG(5, 0, MAX77620_IRQ_LVL2_GPIO_EDGE5),
- REGMAP_IRQ_REG(6, 0, MAX77620_IRQ_LVL2_GPIO_EDGE6),
- REGMAP_IRQ_REG(7, 0, MAX77620_IRQ_LVL2_GPIO_EDGE7),
+ [0] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 0,
+ },
+ [1] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 1,
+ },
+ [2] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 2,
+ },
+ [3] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 3,
+ },
+ [4] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 4,
+ },
+ [5] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 5,
+ },
+ [6] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 6,
+ },
+ [7] = {
+ .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
+ .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
+ .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
+ .reg_offset = 0,
+ .type_reg_offset = 7,
+ },
};
static struct regmap_irq_chip max77620_gpio_irq_chip = {
@@ -42,8 +90,11 @@ static struct regmap_irq_chip max77620_gpio_irq_chip = {
.irqs = max77620_gpio_irqs,
.num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
.num_regs = 1,
+ .num_type_reg = 8,
.irq_reg_stride = 1,
+ .type_reg_stride = 1,
.status_base = MAX77620_REG_IRQ_LVL2_GPIO,
+ .type_base = MAX77620_REG_GPIO0,
};
static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
--
2.1.4
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| From | Laxman Dewangan <ldewangan@nvidia.com> |
|---|---|
| Date | 2016-05-24 15:30 +0200 |
| Subject | [PATCH 2/3] gpio: max77620: Implement gpio_get_direction callback |
| Message-ID | <rCkzg-3M3-35@gated-at.bofh.it> |
| In reply to | #1406169 |
Implement gpio_get_direction() callback for MAX77620 GPIO.
This is useful for debugfs and the userspace ABI.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
drivers/gpio/gpio-max77620.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
index 35f365c..0bb6d93 100644
--- a/drivers/gpio/gpio-max77620.c
+++ b/drivers/gpio/gpio-max77620.c
@@ -9,6 +9,7 @@
*/
#include <linux/gpio/driver.h>
+#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/mfd/max77620.h>
#include <linux/module.h>
@@ -152,6 +153,23 @@ static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
return ret;
}
+static int max77620_gpio_get_direction(struct gpio_chip *gc,
+ unsigned int offset)
+{
+ struct max77620_gpio *mgpio = gpiochip_get_data(gc);
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
+ if (ret < 0) {
+ dev_err(mgpio->dev, "GPIO register read failed: %d\n", ret);
+ return ret;
+ }
+
+ return (val & MAX77620_CNFG_GPIO_DIR_MASK) ?
+ GPIOF_DIR_IN : GPIOF_DIR_OUT;
+}
+
static int max77620_gpio_set_debounce(struct gpio_chip *gc,
unsigned int offset,
unsigned int debounce)
@@ -236,6 +254,7 @@ static int max77620_gpio_probe(struct platform_device *pdev)
mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
mgpio->gpio_chip.get = max77620_gpio_get;
mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
+ mgpio->gpio_chip.get_direction = max77620_gpio_get_direction;
mgpio->gpio_chip.set_debounce = max77620_gpio_set_debounce;
mgpio->gpio_chip.set = max77620_gpio_set;
mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
--
2.1.4
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-05-30 17:10 +0200 |
| Subject | Re: [PATCH 2/3] gpio: max77620: Implement gpio_get_direction callback |
| Message-ID | <rEwZk-5PN-35@gated-at.bofh.it> |
| In reply to | #1406172 |
On Tue, May 24, 2016 at 3:13 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote: > Implement gpio_get_direction() callback for MAX77620 GPIO. > This is useful for debugfs and the userspace ABI. > > Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> > #include <linux/gpio/driver.h> > +#include <linux/gpio.h> No. This is a sign that something is wrong, no driver should include this unless it is using GPIOs as a resource itself. > + return (val & MAX77620_CNFG_GPIO_DIR_MASK) ? > + GPIOF_DIR_IN : GPIOF_DIR_OUT; Just return 0 or 1. The driver-internal API isn't smarter than that. Yours, Linus Walleij
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| From | Laxman Dewangan <ldewangan@nvidia.com> |
|---|---|
| Date | 2016-05-31 08:10 +0200 |
| Subject | Re: [PATCH 2/3] gpio: max77620: Implement gpio_get_direction callback |
| Message-ID | <rEL2i-75S-15@gated-at.bofh.it> |
| In reply to | #1409206 |
On Monday 30 May 2016 08:33 PM, Linus Walleij wrote: > On Tue, May 24, 2016 at 3:13 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote: > >> Implement gpio_get_direction() callback for MAX77620 GPIO. >> This is useful for debugfs and the userspace ABI. >> >> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> >> #include <linux/gpio/driver.h> >> +#include <linux/gpio.h> > No. This is a sign that something is wrong, no driver should include > this unless it is using GPIOs as a resource itself. This is just to use the flag GPIOF_* As you said below, we can use the 0 and 1, there is no need to include header. Will post the v2 patch for this. >> + return (val & MAX77620_CNFG_GPIO_DIR_MASK) ? >> + GPIOF_DIR_IN : GPIOF_DIR_OUT; > Just return 0 or 1. The driver-internal API isn't smarter than that. > Thanks, Laxman
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-05-30 17:10 +0200 |
| Message-ID | <rEwZj-5PN-7@gated-at.bofh.it> |
| In reply to | #1406169 |
On Tue, May 24, 2016 at 3:13 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote: > The GPIO sub modules of MAX77620 offers to configure the GPIO > interrupt trigger level as RISING and FALLING edge. > > Pass this information to regmap-irg when registering for GPIO > interrupts. > > Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Patch applied. Yours, Linus Walleij
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